View MSX340-10PB480_7739472.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

i-cube, inc. [rev. 1.8] 2/28/01 1 msx family data sheet features description the msx? family of sram-based bit-oriented switching devices offer flow-through nrz data rates of up to 300mb/s and registered clock frequencies of up to 150mhz. the i/o buffers (iobs) are individually configurable. the iobs can be connected to each other through the switch matrix, which supports one-to-one and one-to-many connections. the proprietary rapidconfigure parallel interface allows fast configuration of both the iobs and switch matrix. it also allows readback of the device for test and verification purposes. the msx devices also support the industry standard jtag (ieee 1149.1) interface for boundary scan testing. the jtag interface can also be used to download configuration data to the device. a functional block diagram of the msx architecture is shown in figure 1. applications figure 1 msx532 functional block diagram ? sram-based, in-system programmable configurable i/o ports ? individually programmable as input, output, bi-directional, or bus repeater ? mode ? control signals per i/o port: 2 input enables, 2 output enables, 2 global clock inputs and next neighbor clock option ? output data inversion: capable of inverting output signals in flow through mode non-blocking switch matrix ? one-to-one and one-to-many connections ? double-buffered configuration ram cells for simultaneous global updates registered and flow-through data modes ? up to 150 mhz clock frequency in registered mode ? up to 300 mb/s in flow-through mode as fast as 10ns propagation delay in flow- through mode 8ma output current dedicated rapidconfigure ? parallel interface or jtag serial interface available for configuration and readback of msx devices 3.3v operation, lvttl i/o ? s (5v tolerant) msx532 is offered in a 792 tbga package msx340 is offered in a 480 pbga package telecom and datacom switching video switches and servers test equipment clk_0 ie_0 oe_0# clk_1 ie_1 oe_1# i/o block i/o block clk_3 ie_3 oe_3# clk_2 ie_2 oe_2# port 398 to port 266 port 399 to port 531 port 133 to port 265 port 0 to port 132 switch matrix i/o block i/o block jtag signals tck tdi tms trst# tdo rapidconfigure signals rca[9:0] rcb[9:0] rcc[3:0] rci[1:0] rc_clk rc_en# rc_rdy 10 10 4 2 hw_rst# rce update
msx family data sheet 2 [rev. 1.8] 2/28/01 i-cube, inc. (this page intentionally left blank)
i-cube, inc. [rev. 1.8] 2/28/01 3 msx family data sheet contents 1. introduction ................................................................................................................. .......... 7 1.1 switch matrix............................................................................................................... ........ 7 1.2 input and output buffers (iobs).......................................................................................... 8 1.2.1 i/o port function mode ................................................................................................. 8 1.3 control signals............................................................................................................. .......11 1.4 rapidconfigure interface .................................................................................................... 11 1.4.1 signal description........................................................................................................ 11 1.4.2 read and reset commands.......................................................................................... 13 1.4.3 crosspoint programming ............................................................................................. 16 1.4.4 iob configuration programming................................................................................. 16 1.5 jtag interface .............................................................................................................. ..... 18 1.5.1 iob programming........................................................................................................ 18 1.5.2 jtag architecture and shift registers ........................................................................ 20 1.5.3 jtag state machine .................................................................................................... 21 1.5.4 jtag input format ...................................................................................................... 22 1.5.5 jtag instructions ........................................................................................................ 2 2 2. pin description .............................................................................................................. .......24 3. electrical specifications .................................................................................................... ...25 3.1 absolute maximum ratings .............................................................................................. 25 3.2 recommended operating conditions ................................................................................ 25 3.3 pin capacitance ............................................................................................................ ..... 25 3.4 dc electrical specifications .............................................................................................. 26 3.5 ac electrical specifications .............................................................................................. 27 3.6 test circuit and timing diagrams ..................................................................................... 28 4. package and pinout ........................................................................................................... ...33 4.1 msx532 [792 tbga package] pinout .............................................................................. 33 4.2 msx532 [792 tbga package] pinout: by ball sequence ................................................ 34 4.3 msx532 [792 tbga package] pinout: by ball name (alphabetically) ............................ 38 4.4 msx340 [480 pbga package] pinout .............................................................................. 42
msx family data sheet 4 [rev. 1.8] 2/28/01 i-cube, inc. 4.5 msx340 [480 pbga package] pinout: by ball sequence................................................. 43 4.6 msx340 [480 pbga package] pinout: by ball name ...................................................... 46 4.7 792 tbga package dimensions (bottom view) ............................................................... 48 4.8 792 tbga package dimensions (top and side view) ...................................................... 49 4.9 480 pbga package dimensions (bottom view)................................................................ 50 4.10 480 pbga package dimensions (top and side view) ...................................................... 51 4.11 port cross-reference for the msx532 and msx340 ......................................................... 52 4.12 package thermal characteristics........................................................................................ 55 5. power consumption ............................................................................................................ 56 6. component availability and ordering information ......................................................... 57 7. glossary ..................................................................................................................... ........... 58 8. product status definition .................................................................................................... 61
i-cube, inc. [rev. 1.8] 2/28/01 5 msx family data sheet figures figure 1 msx532 functional block diagram ......................................................................................... ........... 1 figure 2 msx switch matrix diagram............................................................................................... ................ 7 figure 3 msx iob block diagram ................................................................................................... ................. 8 figure 4 msx switch configuration signals ........................................................................................ ........... 12 figure 5 msx jtag architecture ................................................................................................... ................. 20 figure 6 jtag state machine...................................................................................................... ..................... 21 figure 7 test circuit and waveform definition .................................................................................... ........... 28 figure 8 registered input and registered output mode timing (iclk and oclk synchronized) ............... 28 figure 9 registered input timing mode............................................................................................ ............... 28 figure 10 registered output timing mode .......................................................................................... .............. 29 figure 11 i/o port timing (flow-through mode).................................................................................... ........... 29 figure 12 input enable timing (flow-through mode) ................................................................................ ....... 29 figure 13 output enable timing ................................................................................................... ..................... 30 figure 14 jtag timing............................................................................................................ .......................... 30 figure 15 rapidconfigure iob or crosspoint read and write cycles .............................................................. 31 figure 16 rapidconfigure reset command cycle..................................................................................... ........ 32
msx family data sheet 6 [rev. 1.8] 2/28/01 i-cube, inc. tables table 1 summary for programmable i/o attributes for msx devices......................................................... 9 table 2 msx global control signals............................................................................................... ............ 11 table 3 rapidconfigure input..................................................................................................... ................. 13 table 4 reset commands ........................................................................................................... .................. 13 table 5 i/o buffer read commands................................................................................................. ........... 14 table 6 iob programming commands ................................................................................................. ....... 17 table 7 iob programming bit functions............................................................................................ ......... 19 table 8 jtag input format ........................................................................................................ ................. 22 table 9 jtag instructions ........................................................................................................ ................... 22 table 10 absolute maximum ratings ............................................................................................... ............ 25 table 11 recommended operating conditions........................................................................................ ...... 25 table 12 pin capacitance ........................................................................................................ ...................... 25 table 13 lvttl dc electrical specifications..................................................................................... ........ 26 table 14 ac electrical specifications for msx532 and msx340................................................................ 27 table 15 msx532 pinout by ball sequence .......................................................................................... ....... 34 table 16 msx532 pinout by ball name .............................................................................................. ......... 38 table 17 msx340 pinout by ball sequence .......................................................................................... ....... 43 table 18 msx340 pinout by ball name .............................................................................................. ......... 46 table 19 port cross-reference for msx532 and msx340 ............................................................................ 52 table 20 package thermal characteristics ......................................................................................... ........... 55 table 22 order information ...................................................................................................... ..................... 57 table 21 component availability .................................................................................................. ................ 57 table 23 revision history........................................................................................................ ...................... 60
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 7 1. introduction 1.1 switch matrix the msx family are sram-based, bit-oriented switching devices. the main functional block of the device is a switch matrix as shown in figure 1. the switch matrix is an x-y routing structure (or grid). each horizontal signal trace is hardwired to a corresponding vertical signal trace as shown by the junction dots. an i/o port pin connects to this horizontal-vertical trace pair through programmable buffer. signal paths through the switch matrix are well balanced, resulting in predictable and uniform pin-to-pin delays. the two sram cells (shown in figure 2) are arranged so that a double buffered scheme can be employed. the active sram cells are responsible for establishing connections in the switch matrix by turning on a pass transistor, while the loading sram cell can be used to store a second configuration that can be transferred to the active sram cell at any time. if the update signal is asserted high, the contents of the loading sram cell are transferred to the active sram cell and the switch matrix connection is either made or broken. the update signal can be used to control when the switch matrix is reconfigured. for instance, as long as the update signal is de-asserted (held low), the loading sram cells for the entire switch matrix could be changed without affecting the current configuration of the switch. when the update signal is asserted high, the entire switch matrix would be reconfigured simultaneously. if the update signal is asserted continuously, all crosspoint programming commands (generated by jtag or rapidconfigure programming cycles) will take effect immediately, since the loading sram cell ? s contents will be transferred directly to the active sram cell. figure 2 msx switch matrix diagram 1 0 2 34 567 i/o port pins permanent connection pass transistor loading sram cell active sram cell data update programmable i/o buffers
msx family data sheet 8 [rev. 1.8] 2/28/01 i-cube, inc. 1.2 input and output buffers (iobs) each signal in the switch matrix is connected to a programmable iob, which is independently configured through either the rapidconfigure or jtag interface. the iob attributes include its signal direction (input, output or bi-directional) and data flow mode (flow-through or registered). the signal can also be inverted at the output. trickle current source (normally <15 a) on the pin side and array side for each i/o port and control pin is used to pull unused or non-driven circuits to a stable high level. figure 3 shows a basic block diagram of an iob with the sources for the three control signals (ie, oe and clk). for any given port number, these three control signals can be selected from one of two sources. the control signals are explained in more detail in the following section. . figure 3 msx iob block diagram 1.2.1 i/o port function mode the following legend describes the various modes of the input or output ports and the specification used by the i-cube development system software for bitstream generation. legend: ax ? switch matrix signal px ? i/o port signal ie ? input enable oe# ? output enable (# means ? active low ? ) clk ? clock switch matrix out in br i/o port clk_in clk_out ie oe# { { v dd vss { next neighbor clk sources clk sources next neighbor {
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 9 table 1 summary for programmable i/o attributes for msx devices symbol i/o port function mnemonic input ? the external signal is buffered from the input port pin to the corresponding switch matrix line. in output ? the internal signal is buffered from the corresponding switch matrix line to the output port pin. in this mode an optional output enable (oe#) can be selected. the default level is logic 0. the output data inversion mode is available to invert the output signal. op registered output ? the external signal at the i/o port is registered into an edge-triggered register within the i/o port. a clock source is required in this mode. an input enable (ie) is available but not required. ri registered output ? the internal signal on the switch matrix line is registered by an edge-triggered register within the i/o port. a clock source is required in this mode. an output enable (oe#) is available but not required. the output data inversion mode is not available to invert the output signal. ro bidirectional transceiver ? in this mode, the i/o buffer acts as a bidirectional transceiver between the i/o port pin and the corresponding switch matrix line. this mode requires an input enable (ie) and output enable (oe#). the output data inversion mode is available to invert the output signal. bt bus repeater ? in the bus repeater mode, the i/o port behaves as a wire (with a non-zero propagation delay). this unique feature patented by i-cube incorporates as self-sensing circuit to determine signal direction and does not require a direction control signal. when multiple i/o ports, configured as ? bus repeater ? , are connected together through the switch matrix to form a single internal node, any (open collector or tristatable) ? low ? (logic ? 0 ? ) external signal appearing at any one of the i/o ports gets repeated (or broadcast) to other i/o ports. for more details, refer to the technical note: ? the bus repeater mode ? br pin side force 0 ? in this output mode, the i/o port pin is forced low (logic 0), regardless of the signal on the corresponding switch matrix line. in this mode an optional output enable (oe#) can be selected. f0 pin side force 1 ? in this output mode, the i/o port pin is forced high (logic 1), regardless of the signal on the corresponding switch matrix line. in this mode an optional output enable (oe#) can be selected. f1 no connect ? in this mode, the i/o port pin is isolated from the switch matrix. this is done by tri-stating both the input and output part of the i/o buffer. nc px ax ie px ax oe# dq px ax ie clk dq clk px ax oe# px ax ie oe# px ax px ax px ax px ax
msx family data sheet 10 [rev. 1.8] 2/28/01 i-cube, inc. array side force 0 ? in this input mode, the switch matrix line is forced low (logic 0), regardless of the signal on the corresponding i/o port. in this mode an optional input enable (ie) can be selected. a0 array side force 1 ? in this input mode, the switch matrix line is forced high (logic 1), regardless of the signal on the corresponding i/o port. in this mode an optional input enable (ie) can be selected. a1 bidirectional transceiver with register input ? this mode combines registered input and buffered output (op). this mode requires a clock source (clk), and input enable (ie) and output enable (oe#). bt & ri bidirectional transceiver with register output ? this mode combines registered output (ro) and buffered input (ie). this mode requires a clock source (clk), and input enable (ie) and output enable (oe#). the output data inversion mode is not available to invert the output signal. bt & ro bidirectional transceiver with register i/o ? this mode combines registered input (ri) and registered output (ro). this mode requires a clock source (clk), and input enable (ie) and output enable (oe#). the output data inversion mode is not available to invert the output signal. bt, ri &ro table 1 summary for programmable i/o attributes for msx devices (continued) symbol i/o port function mnemonic ax px ax px dq ie ax px clk oe dq ie ax px clk oe d 1 q 1 ie ax px clk_in oe clk_op q 0 d 0
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 11 1.3 control signals every port on the msx devices has two available global clock inputs, input enables, and output enables. however, not all ports have access to the same global control signals. there are four global clocks (clk_0 through clk_3), four global input enables (ie_0 through ie_3), and four global output enables (oe_0# through oe_3#). each global control signal is available to half of the ports on the msx device. table 2 below shows the global control signals that are available to each port. 1.4 rapidconfigure interface the msx family of digital crosspoint switches can be configured in either of two ways. both the jtag serial programming interface and the rapidconfigure (rc) parallel interface can assign crosspoint connections and configure i/o buffers (iobs), but jtag is slower. jtag runs reliably up to 8 mhz and requires over twenty cycles to program a single command. the rapidconfigure interface can run at up to 40 mhz and can send a new command on every clock cycle. systems requiring frequent reconfiguration should be designed to use the rapidconfigure interface. rapidconfigure is a 29 signal parallel interface that effectively flattens the serial jtag bitstream. rather than consecutively shifting in twenty or so bits of data to configure an iob or make a crosspoint connection, all of these bits are driven on the rc lines simultaneously and then latched in by the msx device in a single cycle. additionally, the msx rapidconfigure interface has been enhanced to enable reading back of configuration data from the device. the 29 pins are allocated as follows: rca[9:0] = rapidconfigure address a rcb[9:0] = rapidconfigure address b rcc[3:0] = rapidconfigure program variable c rci[1:0] = rapidconfigure instruction bits rc_clk = rapidconfigure clock rc_en# = rapidconfigure cycle enable rc_rdy = read out iob and connect/disconnect status 1.4.1 signal description the rc interface supports four types of operations. two are write operations to the msx (iob configuration or crosspoint programming) and two are read operations (iob and crosspoint configuration read). the rc signals serve different purposes depending upon the type of operation being performed. table 2 msx global control signals msx340 port number msx532 port number input/output clock source 1 input/output clock source 2 input enable 1 input enable 2 output enable 1 output enable 2 ports 0-84 ports 0-132 clk_0 clk_1 ie_0 ie_1 oe_0# oe_1# ports 85-169 ports 133-265 clk_1 clk_2 ie_1 ie_2 oe_1# oe_2# ports 170-254 ports 266-398 clk_2 clk_3 ie_2 ie_3 oe_2# oe_3# ports 255-339 ports 399-531 clk_3 clk_0 ie_3 ie_0 oe_3# oe_0#
msx family data sheet 12 [rev. 1.8] 2/28/01 i-cube, inc. most of the signals on the msx device ? s rc interface are bi-directional. these signals receive data during write operations. during read operations these pins receive data during the first part of the cycle, and then drive the interface in the final part of the cycle. rca[9:0], rcb[9:0], and rcc[0] are bi-directional pins. rcc[3:1], rc_clk, rc_en#, and rci[1:0] are dedicated inputs. rc_rdy is a dedicated output. the rc_clk signal is the strobe that latches write data into the msx device. it synchronizes the signals driven on to the rc interface and determines the rate at which commands can be loaded into the msx device. the msx device latches command data on the falling edge of rc_clk when rc_en# is asserted. rc write operations can be repeated on consecutive clocks simply by keeping the rc_en# signal asserted and providing new commands on the rca, rcb, rcc, and rci signals. rc read operations require four cycles and cannot be performed on back-to-back clocks. rc_en# is an active low signal that indicates the beginning of an rc operation. back-to-back rc write operations may be performed by keeping the rc_en# signal asserted. during rc read operations rc_en# must remain asserted until the cycle is complete. back-to-back rc read operations can be executed simply by keeping rc_en# asserted. the msx device asserts rc_rdy when it has entered the final stage of a read. rc_rdy is asserted on the falling edge of rc_clk, and de-asserted on the next falling edge. the msx device will be driving valid read data on the rc interface when rc_rdy is asserted high. . figure 4 msx switch configuration signals tms tdi tck trst# tdo rapidconfigure j t a g update rce 2 10 10 rca[9:0] rcb[9:0] rcc[0] rcc[3:1] rci[1:0] rc_en# rc_clk rc_rdy 3
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 13 the rc interface specifies that the rci signals be used to determine the type of operation being performed. 1.4.2 read and reset commands when rci[1:0] are equal to 11 a read or reset command is executed (see table 4: reset commands). 1.4.2.1 reset commands rcc[0], rcb[9:0], and rca[9:0] have no function during a reset command and must be written as zeroes. table 3 rapidconfigure input rci[1:0] description 00 force testing command. force commands can force a port to drive either a one or a zero to either the pad or crosspoint array. these commands are generally only used for diagnostic testing. 01 i/o buffer programming command. these commands are used to configure a port as an input or output, registered or not, etc. 10 crosspoint array programming command. crosspoint connections can be made or broken, or an individual port can be reset. 11 read and reset commands. this setting is used to read back configuration data from an iob or crosspoint connection information. it can also be used to reset all of the iobs and the crosspoint array. table 4 reset commands rcc[2:1] description 00 reserved. this is not a valid command. 01 reserved. this is not a valid command. 10 crosspoint array reset. this command will reset the entire crosspoint array, breaking any previously existing connections. 11 crosspoint array and iob reset. this command resets both the iobs and the crosspoint array as described above. 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rci[1:0] rcc[3:0] rcb[9:0] rca[9:0] reset cmd options 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 0 1 reset command read/reset cmd 0
msx family data sheet 14 [rev. 1.8] 2/28/01 i-cube, inc. 1.4.2.2 crosspoint read commands a crosspoint read is used to check whether two ports are connected through the crosspoint array. the two ports are addressed using rca[9:0] and rcb[9:0]. the msx device uses rcc[0] to show whether the two ports are connected. it drives rcc[0] high if the two ports are connected, and pulls rcc[0] low if the two ports are not connected. 1.4.2.3 iob read commands i/o buffer reads are more complicated (see table 5: i/o buffer read commands). the port to be read is addressed using rca[9:0]. the msx device uses rca[9:0] and rcb[9:0] to return all of the configuration data for the particular iob. table 5 i/o buffer read commands signal description rca[0] rca[0] is set to one if the iob is an input. it is zero if the iob is not configured as an input. note that an iob can be configured as an input, output, input and output (in bi-directional mode), or no connect. all iobs default to inputs at power-on reset or following a global iob reset command, so rca[0] will read as a one at reset. rca[1] rca[1] is set to a one if the iob is an output. it is zero if the iob is not configured as an output. if rca[1:0] equal 00 the iob is configured as a no connect. a no connect means that the i/o pin of the msx device is not connected to the crosspoint array. rca[1] will read as a zero at reset. rca[2] rca[2] is set to a one if the iob is configured in bus repeater mode. it is zero if the iob is not in bus repeater mode. bus repeater mode will be disabled by default at reset, so rca[2] will read as a zero. rca[3] rca[3] is set to a one if the iob is configured as a registered input and is assigned to use its input clock 1. it is zero if the iob is not using input clock 1. input clock 1 for each iob will vary depending upon the quadrant of the device in which it resides. rca[3] will read as a zero at reset. rca[4] rca[4] is set to a one if the iob is configured as a registered input and is assigned to use its input clock 2. it is zero if the iob is not using input clock 2. as with input clock 1, the source changes depending upon the quadrant of the device in which the iob resides. rca[4] will read as a zero at reset. rca[5] rca[5] is set to a one if the iob is configured as a registered input and assigned to use next neighbor clocking. it is zero if next neighbor clocking is disabled. next neighbor clocking allows the iob to be registered using the next higher numbered port number signal as its input clock source. port 100 on the msx devices can use the signal from port 101 for its input clock if this mode is enabled. port 531 ? s next neighbor is port 0. next neighbor clocking will be disabled by default at reset, so rca[5] will read as a zero. 1 1 1 0 0 rci[1:0] rcc[3:0] rcb[9:0] rca[9:0] cross point read 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 0 1 read command read/reset cmd 0 0 port #1 port #2 1 1 1 1 0 rci[1:0] rcc[3:0] rcb[9:0] rca[9:0] i/o buffer config read 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 0 1 read command read/reset command 0 0 i/o buffer address 0 0 0 0 0 0 0 0 0 0
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 15 rca[6] rca[6] is set to a one if the iob is configured as a registered output and is assigned to use its output clock 1. it is zero if the iob is not using output clock 1. as with input clock 1 and 2, the output clocks will vary depending upon the quadrant of the device in which the iob resides. in the case of the msx devices, the output clock 1 and input clock 1 for each iob have the same source, and the output clock 2 and input clock 2 do as well. rca[6] will read as a zero at reset. rca[7] rca[7] is set to a one if the iob is configured as a registered output and is assigned to use its output clock 2. it is zero if the iob is not using output clock 2. as with output clock 1, the source changes depending upon the quadrant of the device in which the iob resides. rca[7] will read as a zero at reset. rca[8] rca[8] is set to a one if the iob is configured as a registered output and is assigned to use next neighbor clocking. it is zero if next neighbor clocking is disabled. next neighbor clocking allows the iob to be registered using the next higher numbered port number signal as its output clock source. port 100 on the msx devices can use the signal from port 101 for its output clock if this mode is enabled. port 531 ? s next neighbor is port 0. next neighbor clocking will be disabled by default at reset, so rca[8] will read as a zero. rca[9] rca[9] is set to a one if the iob is assigned to use input enable 1. it is zero if the iob is not using input enable 1. all bi-directional iobs must use one of the dedicated input enable pins (ie_0, ie_1, ie_2, or ie_3) to enable the iob to drive data into the crosspoint array. as with the dedicated clock pins, each iob can access two input enable signals, which will vary depending upon the quadrant of this chip in which the iob resides. rca[9] will read as a zero at reset. rcb[0] rcb[0] is set to a one if the iob is assigned to use input enable 2. it is zero if the iob is not using input enable 2. rcb[0] will read as a zero at reset. rcb[1] rcb[1] is set to a one if the iob is assigned to use output enable 1. it is zero if the iob is not using output enable 1. all bi-directional iobs must use one of the dedicated output enable pins (oe_0#, oe_1#, oe_2#, or oe_3#) to enable the iob to drive the pin of the device. as with the dedicated clock pins, each iob can access two output enable signals, which will vary depending upon the quadrant of the chip in which the iob resides. rcb[1] will read as a zero at reset. rcb[2] rcb[2] is set to a one if the iob is assigned to use output enable 2. it is zero if the iob is not using output enable 2. rcb[2] will read as a zero at reset. rcb[6:3] rcb[6:3] are reserved. rcb[7] rcb[7] is set to a one if the iob is configured as an inverted output. it is zero if the iob is not configured as an inverted output. the output of any iob may be inverted so long as it is not a registered output or running in bus repeater mode. rcb[7] will read as a zero at reset. rcb[8] rcb[8] is set to a one if the iob is configured as a registered input and is using an inverted input clock source. it is zero if it is not using an inverted input clock. inputs can use any of the three clock sources described above and may invert that clock if desired. rcb[8] will read as a zero at reset. rcb[9] rcb[9] is set to a one if the iob is configured as a registered output and is using an inverted output clock source. it is zero if it is not using an inverted output clock. outputs can use any of the three clock sources described above and may invert that clock if desired. rcb[9] will read as a zero at reset. table 5 i/o buffer read commands (continued) signal description
msx family data sheet 16 [rev. 1.8] 2/28/01 i-cube, inc. 1.4.3 crosspoint programming connections between ports through the crosspoint array can be quickly made or broken using the rc interface. the two ports to be connected or disconnected are addressed using rca[9:0] and rcb[9:0]. rcc[1] controls whether a connection is made or broken. the two ports are connected when rcc[1] is set to zero, and disconnected when rcc[1] is set to one. unlike iob programming commands, which take effect immediately upon execution of the command, crosspoint connections will only be made if the update signal is asserted high. the crosspoint programming command loads the loading sram cell in the selected crosspoint array location with a one (in the case of a new connection) or a zero (to break an existing connection). if the update signal is asserted, the loading sram cells contents are immediately transferred to the active sram cell and the connection is made or broken. however, if the update signal is held low, the new connection will not be made. the update signal can be used to control when the switch matrix connections are reconfigured. 1.4.4 iob configuration programming each port can be fully configured in a single rapidconfigure cycle. the figure below shows how an iob is programmed using all of the signals on the rc interface. the following table shows how each control bits (rcc[3:0] and rcb[9:0]) are used. during an iob programming command the rca[9:0] signals address the port to be programmed (see table 6: iob programming commands). 1 0 0 1 0 rci[1:0] rcc[3:0] rcb[9:0] rca[9:0] connect/disconnect (0-connect, 1-disconnect) 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 0 1 crosspoint program 0 port #1 port #2 0 1 rci[1:0] rcc[3:0] rcb[9:0] rca[9:0] 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 0 1 i/o buffer configuration 0 i/o buffer address bus repeater enable input/output select output enable select input enable select output clock source input clock source invert output inverted input clock inverted output clock
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 17 table 6 iob programming commands signal description rcc[3] bus repeater enable. setting this bit to a one enables the iob to operate in bus repeater mode, a special bi- directional mode. when zero the iob will not operate in bus repeater mode. when programming an iob to use bus repeater mode, all of the other control bits must be set to zeroes. attempting to combine other iob options with bus repeater mode may lead to unpredictable results. rcc[2:1] input/output select. these two bits are used to configure the iob as an input, output, input/output (bi- directional mode), or no connect. when operating in bi-directional mode it is critical that the port be assigned input and output enables so that it can be tri-stated appropriately to avoid contention. rcc[2:1] function 00 no connect 01 input 10 output 11 input / output for bi-directional mode rcc[0] and rcb[9] output enable select. these two bits are used to select from the two available active low global output enables. the output will be allowed to drive when its assigned output enable is asserted. an output port will be tri-stated when its assigned output enable is de-asserted. when both output enables are selected, the two available active low output enable signals are and ? s together to form the port ? s combined output enable signal. rcc[0], rcb[9] function 00 no output enable selected 01 output enable 1 10 output enable 2 11 both output enables rcb[8:7] input enable select. these bits are used to assign a port one of the two available global input enable signals. an input port will drive into the crosspoint array when its assigned input enable is asserted. when both input enables are selected, the two available input enable signals are or ? d together to form the port ? s combined input enable signal. rcb[8:7] function 00 no input enable selected 01 input enable 1 10 input enable 2 11 both input enables rcb[6:5] output clock source. these bits are used to select a clock source for a registered output port. each iob can select from one of two global clock inputs, or can use next neighbor clocking. next neighbor clocking uses the signal on the next higher numbered port as a clock source. if no clock source is assigned to an output port, it will operate in flow-through mode. rcb[6:5] function 00 no output clock source selected 01 output clock source 1 10 output clock source 2 11 next neighbor output clock source
msx family data sheet 18 [rev. 1.8] 2/28/01 i-cube, inc. 1.5 jtag interface the dedicated jtag tap interface is designed in compliance with the ieee-1149.1. the standard interface has five pins: test data out (tdo), test mode select (tms), test data in (tdi), test reset (trst#), and test clock (tck) which allow boundary scan testing as well as device configuration and verification. data on the tdi and tms pins are clocked into the device on the rising edge of the tck signal, while the valid data appears on the tdo pin after the falling edge of tck. for more detailed information on jtag programming, refer to the msx family register programming manual . 1.5.1 iob programming the jtag iob data register where data is held, is used to program the iob. this register is used with the jtag interface only. the jtag iob data register is 20 bits wide. power on reset, rapidconfigure reset, hardware reset, and jtag reset programs all ports as inputs. jtag can be reset via the trst# pin or by clocking five consecutive ones to the tms pin. the hw_rst# (hardware reset) pin resets and breaks all connections in the crosspoint array to all no-connects, and the iobs to inputs. table 7 lists the bits and their function in jtag mode. these are internal bits as shifted into the iob data register for iob programming. rcb[4:3] input clock source. these bits are used to select a clock source for a registered input port. each iob can select from one of two global clock inputs, or can use next neighbor clocking. next neighbor clocking uses the signal on the next higher numbered port as a clock source. if no clock source is assigned to an input port, it will operate in flow-through mode. rcb[6:5] function 00 no input clock source selected 01 input clock source 1 10 input clock source 2 11 next neighbor input clock source rcb[2] invert output. if an output port is programmed with this bit set to a one, the output of the port will be inverted. if this bit is zero, the output will not be inverted. outputs may not be inverted when operating in bus repeater mode or in registered output mode. rcb[1] inverted input clock. when this bit is set to a one, the registered input port ? s selected clock source will be inverted. when zero the input clock source will not be inverted. rcb[0] inverted output clock. when this bit is set to a one, the registered output port ? s selected clock source will be inverted. when zero the output clock source will not be inverted. table 6 iob programming commands (continued) signal description
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 19 notes: 1. if both ie1 and ie2 are selected, the two are assigned an or function to form the ie. either can be ? 1 ? to enable the input. 2. if both oe1# and oe2# are selected, active low signals are assigned an and function to form the resulting oe#. either can be ? 0 ? to enable the output. table 7 iob programming bit functions bit number iob function description 0 input (in) input pin data to drive array 1 output (op) output array data to pin 2 bus repeater (br) low array signal, drive pin low low pin signal, drive array low 3 reg in clock 1 selects reg. in iob, clock 1 4 reg in clock 2 selects reg. in iob, clock 2 5 reg in clk neighbor selects reg. in iob, neighbor 6 reg out clock 1 selects reg. out iob, clock 1 7 reg out clock 2 selects reg. out iob, clock 2 8 reg out clk neighbor selects reg. out iob, neighbor 9 input enable 1 (ie1) select input enable 1 1 10 input enable 2 (ie2) select input enable 2 1 11 output enable 1 (oe1) select output enable 1 2 12 output enable 2 (oe2) select output enable 2 2 13 force 1 force iob output pin to a 1 14 force 0 force iob output pin to a 0 15 array 1 force iob array to a 1 16 array 0 force iob array to a 0 17 invert output output data is inverted. this operation is invalid in bus repeater mode and register output mode 18 invert input clock invert the clock to the input register 19 invert output clock invert the clock to the output register
msx family data sheet 20 [rev. 1.8] 2/28/01 i-cube, inc. 1.5.2 jtag architecture and shift registers figure 5 msx jtag architecture jtag data register - 1 bit boundary scan register (576 x 2 = 1152bits) tap controller tdi instruction register - 16 bits tdo tms tck iob data register - 20 bits device identification register - 32 bits bypass register - 1 bit trst# mode control register - 2 bits jtag address register - 10 bits buf mux iob copy register - 20 bits
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 21 1.5.3 jtag state machine figure 6 jtag state machine test logic reset run test/ idle select dr scan capture dr shift dr exit 1 dr pause dr exit 2 dr update dr select ir scan capture ir shift ir exit 1 ir pause ir exit 2 ir update ir 0 0 0 0 0 0 0 0 0 1 11 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1
msx family data sheet 22 [rev. 1.8] 2/28/01 i-cube, inc. 1.5.4 jtag input format 1.5.5 jtag instructions table 8 jtag input format instruction control address bit number 1514131211109876 543210 bit name i3 i2 i1 i0 c1 c0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 table 9 jtag instructions i3 i2 i1 i0 instruction description 1 1 1 1 bypass places device in a mode to pass tdi data to tdo with one clock delay. used for programming and testing devices through serial connected jtag controls. 1 1 1 0 control register shifts data in and out of the control register. capture, shift, and write the control register. 1 1 0 1 io buffer and crosspoint array reset, device id out resets iobs for the ports to input and clear all ports to disconnect. the device id is serialized out to tdo. the instruction serialized out is the reset instruction during the instruction phase. update is forced to the crosspoint array. 1 1 0 0 device id out serialize the device id and revision history out to tdo. id for the msx is 0x0000a89f. 1 0 1 1 set the jtag address register set the 10-bit jtag address register with the lower ten bits of the jtag instruction register. the lower ten bits of the jtag address register become the ? b ? address for crosspoint access. 1 0 1 0 access the crosspoint array and update array read or write the crosspoint addressed by the lower ten bits of the jtag instruction (a address) and the jtag address register or address counter (b address). read data is shifted out on tdo. c1 c0=0 0 read switch with a and b address. increment ? b ? address with each shiftdr. c1 c0=0 1 connect switch at location addressed with a and b. increment ? b ? address with each shiftdr. activate with updatedr. c1 c0=1 0 disconnect switch at location addressed with a and b. increment ? b ? address with each shiftdr. activate with updatedr. c1 c0=1 1 force update of switch array shadow register. activate with updatedr. 1 0 0 1 disconnect a port in the crosspoint array disconnect all ports from the port addressed by the lower ten bits of the jtag instruction. the addressed port is reset to disconnect. the programmed state of the iob is not changed. 1 0 0 0 clear the crosspoint array clear the crosspoint array at no-connect. leave the iobs unchanged. 0 1 1 1 shift the io buffer data register shift twenty bits of data into and out of the iob data register. the data is used to program the iobs. parallel shift twenty bits into iob copy register. 0 1 1 0 shift out the iob copy register shifts twenty bits of data out of the iob copy register. data is either the iob data register shifted in by instruction 0111 or the last jtag iob read data.
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 23 0 1 0 1 access an iob read or write the iob addressed with the lower ten bits of the jtag instruction. read data is placed in the twenty-bit iob copy register. write data for the iob is from the iob data register. c1 c0=0 0 read an iob date into the copy register. c1 c0=0 1 write an iob with data in iob data register. 0100 not used. 0 0 1 1 test mode only for programming device with rapidconfigure through jtag i-cube only - internal test mode to test rapidconfigure through jtag. 0 0 1 0 crosspoint array write testing, write one location per shiftdr instruction address=lowerlimit=a, address register=upper limit=b. c1=1, c0=1 connect all ports in address range c1=1, c0=0 connect pattern=a[1] xor b[1] c1=0, c0=0 connect pattern=a[4] c1=0, c0=1 connect pattern=not (a[1] xor b[1]). compliment address limits, address is complimented to test a-high port to b-low port connections. other three patterns test opposite. the number of cycles=(sum of (x=1), where x=low limit to x=high limit) - 1 0 0 0 0 sample/preload extest external scan tests for interconnect testing. 0 0 0 1 sample/preload extest external scan tests for interconnect testing. table 9 jtag instructions (continued) i3 i2 i1 i0 instruction description
msx family data sheet 24 [rev. 1.8] 2/28/01 i-cube, inc. 2. pin description pin name type description p[531:000] bi-directional input/output signals. oe[3:0]# input global output enables. each output enable can control two of the four i/o banks. signal msx532 connected i/o ? s msx340 connected i/o ? s oe_0# p399-p531, p000-p132 p255-p339, p000-p084 oe_1# p000-p132, p133-p265 p000-p084, p085-p169 oe_2# p133-p265, p266-p398 p085-p169, p170-p254 oe_3# p266-p398, p399-p531 p170-p254, p255-p339 ie[3:0] input global input enables. each input enable can control two of the four i/o banks. signal msx532 connected i/o ? s msx340 connected i/o ? s ie_0 p399-p531, p000-p132 p255-p339, p000-p084 ie_1 p000-p132, p133-p265 p000-p084, p085-p169 ie_2 p133-p265, p266-p398 p085-p169, p170-p254 ie_3 p266-p398, p399-p531 p170-p254, p255-p339 update input global update clk[3:0] input global clocks. each clock can control two of the four i/o banks. signal msx532 connected i/o ? s msx340 connected i/o ? s clk_0 p399-p531, p000-p132 p255-p339, p000-p084 clk_1 p000-p132, p133-p265 p000-p084, p085-p169 clk_2 p133-p265, p266-p398 p085-p169, p170-p254 clk_3 p266-p398, p399-p531 p170-p254, p255-p339 hw_rst# input hardware reset. rce input rapidconfigure mode select. determines which programming mode that the device powers up in. 0 = jtag mode (rapidconfigure disabled) 1 = rapidconfigure mode (jtag, iob, crosspoint programming disabled) rc pins rc_clk input rapidconfigure clock. rc_en# input rapidconfigure cycle enable. rca[9:0] bi-directional rapidconfigure address a. rcb[9:0] bi-directional rapidconfigure address b. rcc[0] bi-directional rapidconfigure program variable c. rcc[3:1] input rapidconfigure program variable c. rci[1:0] input rapidconfigure instruction bits. rc_rdy output read out iob and connect/disconnect status. jtag pins tck input jtag test clock. tdi input jtag test data in. tdo output jtag test data out. tms input jtag test mode select. trst# input jtag test reset. power and ground pins v dd power +3.3v power for the chip. v ss ground ground for the chip. tie these pins to system ground.
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 25 3. electrical specifications 3.1 absolute maximum ratings 3.2 recommended operating conditions 3.3 pin capacitance 1. exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. a maximum undershoot of 2v for a maximum duration of 20 ns is acceptable. overshoot to 5.5v is acceptable. 3. all inputs are 5v tolerant with the v dd pin at 3.3v. 4. capacitance measured at 25 c. sample tested only. 5. measured using human body model. table 10 absolute maximum ratings 1 symbol parameter limits units v dd supply voltage -0.3 to +3.6 v v in 2 supply voltage (inputs) -0.3 to +5.5 3 v t j junction temperature +150 c t stg storage temperature -65 to +150 c p max maximum power dissipation tbd w esd 5 electrostatic discharge 2000 v table 11 recommended operating conditions symbol parameter limits units v dd supply voltage +3.0 to +3.6 v t a operating temperature 0 to +70 c table 12 pin capacitance 4 symbol parameter limits units c clk input capacitance 10 pf c port i/o signal port capacitance 8 pf
msx family data sheet 26 [rev. 1.8] 2/28/01 i-cube, inc. 3.4 dc electrical specifications (t a = 0 c to 70 c, v dd = 3.3v 10%) 1. see section 5 for dynamic power consumption calculation. table 13 lvttl dc electrical specifications symbol parameter conditions min max units v ih high-level input ports are 5v tolerant 2.0 5.25 v v il low-level input ports are 5v tolerant -0.3 0.8 v v oh high-level output v dd = min v dd = 3.00 i oh = -4ma 2.4 v dd + 0.3 v v ol low-level output v dd = min v dd .pad = 3.00 i ol = 8ma 0.4 v il ih , il il input leakage for non- programmable i/o pins v dd = max 0.0 < in < v dd +5 -100 ? il oz tristate leakage output off state v dd = max 0.0 < in < v dd +5 -100 ? i osh short circuit current, out = high v dd = max v 0 = gnd -80 ma i osl short circuit current, out = low v dd = max v 0 = v dd 50 ma supply current i ddq quiescent supply current v dd = max 50 ma q ddd 1 dynamic supply current v dd = max. no load, one input cycling @ 50% duty cycle 0.25 ma/mhz
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 27 3.5 ac electrical specifications (t a = 0 c to 70 c, v dd = 3.3v 10%) note ? refer to figure 7 for ac test conditions. table 14 ac electrical specifications for msx532 and msx340 symbol parameter ? 10 ? 20 units min max min max r data nrz data rate 300 150 mb/s f rio registered input/output clock frequency 150 75 mhz t w_rio registered clock pulse width, high or low 2 2 ns t s_ri registered input setup time to clock 3.5 3.5 ns t s_ro registered output setup time to clock 9.5 9.5 ns t h_ri registered input clock to hold data 0 0 ns t h_ro registered output clock to hold data 0 0 ns t co_ro registered output clock to data out valid 11 11 ns t co_ri registered input clock to data out valid 15 24 ns t phl , t plh one way signal propagation delay, fanout = 1 10 20 ns t mc delta additional delay per output multicast (mc) mode 0.25 2 ns t w+ input flow-through positive pulse width t w- input flow-through negative pulse width t sk skew 1.5 2 ns t pzh_it, t pzl_it input enable to valid data 15 20 ns t pzh_ot, t pzl_ot output enable to valid data 7.5 7.5 ns t pzh_ot, t pzl_ot output enable to high z state 7.5 7.5 ns t rc rapidconfigure clock period 20 20 ns t w+_rc t w-_rc rapidconfigure clock pulse width 5 5 ns t s_rc rapidconfigure address setup to rc clock 1 1 ns t h_rc rapidconfigure address hold time to rc clock 4 4 ns t p_rc read back access time 9 9 ns t p_rd rc_rdy to readback data 4 4 ns t p_ud update of crosspoint to data out 10 10 ns f jtag jtag clock frequency (tck) 8 8 mhz t w_jtag jtag clock pulse width (tck) at 20 mhz cycle 40 60 40 60 ns t s_jtag jtag setup time 4 4 ns t h_jtag jtag hold time 0 0 ns t p_jtag jtag clock to output data valid (tdo) 10 10 ns
msx family data sheet 28 [rev. 1.8] 2/28/01 i-cube, inc. 3.6 test circuit and timing diagrams figure 7 test circuit and waveform definition figure 8 registered input and registered output mode timing (iclk and oclk synchronized) figure 9 registered input timing mode 50 ? v dd .pad 800 ? 35pf* pulse generator d.u.t. vin vout 400 ? 3.3v * load capacitance includes jig and probe capacitance. t plz /t pzl closed all others open parameter tested switch position 3.0v 1.5v 0v t r t f t r t f t w 90% 10% negative pulse 3.0v 1.5v 0v 90% 10% positive pulse t f = 2 ns (max) t r = 2 ns (max) d n d n+1 t co_rio d n-2 d n d n-1 outport t w_rio t w_rio t s_rio t h_rio clk inport dq out port dq clkin inport switch matrix ri ro clkout t co_ri outport t w_ri t w_ri t s_ri t h_ri clk inport d n-1 d n d n+1 d n d n+1 ri op inport outport switch matrix dq clk
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 29 figure 10 registered output timing mode figure 11 i/o port timing (flow-through mode) figure 12 input enable timing (flow-through mode) t co_ro d n-1 d n d n+1 d n d n+1 outport t w_ro t w_ro t s_ro t h_ro clk inport inport out port ro in switch matrix dq clk 1.5v inport 1 inport 2 outport 1 outport 2 t sk t sk t plh t w+ t phl inport 1 in op outport 1 switch matrix inport 2 outport 2 ie outport t pzh_it t pzl_it inport ie in op outport inport switch matrix t w-
msx family data sheet 30 [rev. 1.8] 2/28/01 i-cube, inc. figure 13 output enable timing figure 14 jtag timing oe# outport t pzh_ot t pzl_ot t plz_ot t phz_ot v ol + 0.3v v oh - 0.3v v ol v oh inport oe in op outport inport switch matrix t p_jtag t s_jtag t h_jtag t w_jtag t w_jtag tck tdi, tms tdo
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 31 figure 15 rapidconfigure iob or crosspoint read and write cycles rc_clk rc_en# rci[1:0] rcc[3:0] rcb[9:0] rca[9:0] rc_rdy rapidconfigure iob or crosspoint write cycle cmd data 1 cmd data 1 cmd data 1 cmd data 1 rapidconfigure iob or crosspoint read cycle rc data latched on falling edge of rc_clk cmd data 2 cmd data 2 cmd data 2 cmd data 2 cmd data 3 cmd data 3 cmd data 3 cmd data 3 rc_clk rc_en# rci[1:0] rcc[3:0] rcb[9:0] rca[9:0] rc_rdy cmd data cmd data cmd data cmd data rcc[0] for crosspoint read rcb[9:0] for iob read rca[9:0] for iob read rc read cmd latched on falling edge of rc_clk output port t rc t s_rc t w+_rc t w-_rc t hrc t p_ud t h_rc t p_rd t s_rc t p_ud update
msx family data sheet 32 [rev. 1.8] 2/28/01 i-cube, inc. figure 16 rapidconfigure reset command cycle rc_clk rc_en# rci[1:0] rcc[3:0] rcb[9:0] rca[9:0] rc_rdy reset cmd data cmd data cmd data rc read cmd latched on falling edge of rc_clk t h_rc reset cmd data
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 33 4. package and pinout 4.1 msx532 [792 tbga package] pinout 37 38 39 vss vss c d e f g h j k l m n p r t u v w y aa ab ac ad ap ar at au rca1 vss vss ie_1 p135 p145 p068 vdd p019 vdd vss rcc3 p510 vdd vdd vdd vss vss oe_3# vss p373 vdd p265 p279 vss vss vss p166 p191 vss vdd p027 vdd p078 p404 p380 vdd p331 p469 vdd p520 vdd vss p198 vss p151 rca9 rca7 rcb1 rca8 rca2 rca6 rca3 vss vss ie_0 rcb3 vss vdd rcb6 oe_0# tdo p521 p523 p525 p527 update p526 p528 p530 rce rc_en# rci0 vss rcc2 rcb9 rcb8 rcb7 p499 vss vdd vdd p504 p502 p511 p506 vss vdd vdd p513 p512 p518 p517 vss p489 p500 p494 p503 p488 vdd p495 p471 p473 p475 vdd vdd p476 p479 p480 p481 p482 vss vdd p484 p485 p493 p492 p468 p466 p422 vdd p424 vdd p421 vdd vss vss vss p417 p416 ie_3 p414 p409 p408 c d e f g h j k l m n p r t u v w y aa ab ac ad ap ar at au 1234567891011121314151617181920212223242526 tck p004 p005 vdd rc_rdy tms p032 p035 p003 tdi p029 p028 p030 vdd vdd p023 p025 p018 p009 p014 vdd vdd p020 p021 p011 p008 p015 p010 p399 p396 p397 vdd p395 p393 p391 p389 vdd vdd p385 p384 p381 p378 p379 vdd p364 p363 p361 p360 p358 vdd p357 p356 p352 p350 p351 vdd p346 p347 p341 p340 p369 p386 p376 p370 p374 p411 p371 vdd vdd p398 p402 p353 p367 vdd p388 p403 p405 p413 p041 vss vss oe_1# p189 p188 p130 p142 p083 p079 p132 vdd vdd vdd vss p082 p169 vdd p170 vdd vdd p073 p072 p069 p077 p076 p067 vdd p062 p063 p057 p056 vdd p048 p059 p053 p052 p046 p047 p049 vdd p058 p066 p042 p036 p038 vdd vdd p043 vdd p039 p158 p185 p184 p180 p187 p160 vss p150 p155 p154 vdd p149 vdd p181 p179 p178 p172 p174 p176 p148 p146 p138 p143 p144 vdd clk_1 p139 p171 p163 p164 p167 p161 p157 vdd vdd p343 p342 p337 p336 p330 p332 p333 vdd vdd p327 vss p277 p275 p280 p281 p215 p219 p218 p223 p213 p214 p216 vdd p224 p225 vdd p222 p200 vss p204 p207 vss vss p266 p326 p270 p272 vdd p273 p196 vdd p205 p202 p194 p195 p190 p199 vdd p208 p209 p211 msx532 in 792 tbga top view p134 av vss vss vss vss p415 p412 p406 av p394 p392 p382 p377 p365 p359 p354 p348 p349 p368 vss p375 p401 p344 p339 p335 oe_2# vss p328 aw vss vss vss vss p410 p407 vss aw vss p390 p383 vss p362 vss p355 vss p345 p366 p387 p372 p400 vss p338 p334 p284 vss p329 vss vss b vss hw_rst# b p006 p001 p034 p002 p031 p024 p022 p017 p013 p040 vss vss p126 p081 p070 p074 p060 p051 p054 p061 p064 p045 vss vss a vss trst# a p007 p000 p037 vss p033 p026 vss p016 p012 vss vss vss p125 p080 p071 p075 p065 p050 p055 vss vss p044 rca0 p418 rcb2 rca5 vss vss rcb5 p522 p529 rc_clk rcc1 p505 p509 p515 p516 p498 p496 p472 p477 p478 p486 p491 p467 p420 vss vss vss vss vss vss vss vss p137 vdd vss p162 vdd p212 p220 vdd p173 vdd p133 vss vss vss p186 vss p168 vdd p182 p183 p152 p153 p147 p177 vdd p175 p141 p140 p136 p165 p156 p159 p192 vss vss vdd p221 p210 p217 p227 vdd p203 p201 p276 vss vss p274 p197 p193 p206 vdd vss p278 vss clk_2 p128 p131 vss vss p296 vdd ie_2 p319 p310 p312 p313 p315 vdd p306 p309 p302 p304 p305 p297 p299 p298 p290 p293 vdd vdd p303 p316 vdd vdd p292 p295 p289 p286 p283 p282 p285 p318 p314 p308 p307 p301 p294 p288 p287 p320 p317 p311 vss p300 vss p291 vss p321 p323 p322 p325 p324 vss p109 p098 vss p093 p092 p095 p094 p096 p100 p101 p103 p102 p104 p105 p108 p111 p110 p112 p113 p089 p091 vss p090 p118 p119 p115 p114 p121 p120 p123 p122 p124 vdd p097 vdd p107 vdd p117 vdd p127 vdd p099 vdd p106 vdd p116 vdd p129 vss p085 p084 p087 p086 p088 ae af ag ah aj ak al am an vss vss p251 vdd vss p261 vss p459 p458 p461 p460 p464 vss p449 vdd p454 vdd p451 p453 p450 vdd p430 p432 vss p435 p436 p433 vdd vdd p440 p441 p442 p447 p443 vdd vdd vss p429 p423 p425 ae af ag ah aj ak al am an p229 p226 p230 p232 p255 p260 p263 vdd vdd p254 p256 p258 p264 p267 p271 vss vdd p241 p244 p247 p236 p240 p243 p242 p233 p235 vdd p237 p249 vss p250 p252 p462 p457 p455 p431 p437 p438 p444 p448 p426 p231 vdd vdd p238 p228 vdd p259 p262 p253 p257 p269 p268 p245 vdd p239 p234 p246 p248 27 28 29 30 31 32 33 34 35 36 37 38 39 123456789101112131415161718192021222324252627282930313233343536 vss clk_0 vss vss rca4 rcb0 rcb4 p524 p531 rci1 rcc0 p507 p508 p514 p519 p501 p490 p497 p470 p474 p483 p487 p465 p456 p463 vss p419 vss vss p446 p452 p428 p434 p439 p445 p427 clk_3 vss
msx family data sheet 34 [rev. 1.8] 2/28/01 i-cube, inc. 4.2 msx532 [792 tbga package] pinout: by ball sequence table 15 msx532 pinout by ball sequence ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name a1 vss b1 vss c1 vss d1 vss e1 rca6 f1 rcb1 a2 vss b2 vss c2 vss d2 rca1 e2 rca3 f2 rca8 a3 vss b3 vss c3 vss d3 vss e3 rca0 f3 rca5 a4 vss b4 clk_0 c4 vss d4 vss e4 vss f4 rca4 a5 trst# b5 hw_rst# c5 ie_0 d5 vss e5 vss f5 rca2 a6 p000 b6 p001 c6 tms d6 rc_rdy e6 oe_0# f6 vdd a7 vss b7 p002 c7 p003 d7 tck e7 tdo f7 tdi a8 p007 b8 p006 c8 p004 d8 p005 e8 v dd f8 v dd a9 p012 b9 p013 c9 p010 d9 p011 e9 p008 f9 p009 a10 p016 b10 p017 c10 p015 d10 p014 e10 v dd f10 v dd a11 vss b11 p022 c11 p020 d11 p021 e11 p018 f11 p019 a12 p026 b12 p024 c12 p025 d12 p023 e12 vdd f12 v dd a13 p033 b13 p031 c13 p030 d13 p028 e13 p029 f13 p027 a14 p037 b14 p034 c14 p035 d14 p032 e14 v dd f14 v dd a15 vss b15 p040 c15 p041 d15 p039 e15 p038 f15 p036 a16 p044 b16 p045 c16 p042 d16 p043 e16 vdd f16 v dd a17 p050 b17 p051 c17 p048 d17 p049 e17 p047 f17 p046 a18 p055 b18 p054 c18 p052 d18 p053 e18 v dd f18 v dd a19 vss b19 p061 c19 p058 d19 p059 e19 p056 f19 p057 a20 p065 b20 p060 c20 p063 d20 p062 e20 v dd f20 v dd a21 vss b21 p064 c21 p066 d21 p067 e21 p069 f21 p068 a22 p071 b22 p070 c22 p072 d22 p073 e22 v dd f22 v dd a23 p075 b23 p074 c23 p077 d23 p076 e23 p079 f23 p078 a24 p080 b24 p081 c24 p083 d24 p082 e24 v dd f24 v dd a25 vss b25 p085 c25 p084 d25 p087 e25 p086 f25 p088 a26 p089 b26 p091 c26 p090 d26 p093 e26 v dd f26 v dd a27 p092 b27 p095 c27 p094 d27 p096 e27 p097 f27 p099 a28 p098 b28 p100 c28 p101 d28 p103 e28 v dd f28 v dd a29 vss b29 p102 c29 p104 d29 p105 e29 p107 f29 p106 a30 p109 b30 p108 c30 p111 d30 p110 e30 v dd f30 v dd a31 p112 b31 p113 c31 p115 d31 p114 e31 p117 f31 p116 a32 p119 b32 p118 c32 p120 d32 p121 e32 v dd f32 v dd a33 vss b33 p123 c33 p122 d33 p124 e33 p127 f33 p129 a34 p125 b34 p126 c34 p130 d34 p132 e34 p135 f34 v dd a35 vss b35 p128 c35 p133 d35 vss e35 vss f35 p137 a36 vss b36 p131 c36 vss d36 vss e36 vss f36 p136 a37 vss b37 vss c37 vss d37 vss e37 p134 f37 clk_1 a38 vss b38 vss c38 vss d38 ie_1 e38 oe_1# f38 p139 a39 vss b39 vss c39 vss d39 vss e39 p142 f39 p145
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 35 g1 vss h1 rcb7 j1 vss k1 rce l1 p526 m1 p521 g2 rcb3 h2 rcb6 j2 rcc2 k2 rc_en# l2 p528 m2 p523 g3 rcb2 h3 rcb5 j3 rcc1 k3 rc_clk l3 p529 m3 p522 g4 rcb0 h4 rcb4 j4 rcc0 k4 rci1 l4 p531 m4 p524 g5 rca9 h5 v dd j5 rcb9 k5 rci0 l5 p530 m5 p525 g6 rca7 h6 v dd j6 rcb8 k6 rcc3 l6 update m6 p527 g34 p138 h34 v dd j34 p150 k34 p157 l34 p163 m34 v dd g35 p141 h35 v dd j35 p152 k35 p156 l35 p162 m35 v dd g36 p140 h36 p147 j36 p153 k36 p159 l36 p165 m36 p168 g37 p143 h37 p149 j37 p155 k37 p158 l37 p164 m37 p169 g38 p144 h38 p148 j38 p154 k38 p160 l38 p167 m38 p171 g39 p146 h39 p151 j39 vss k39 p161 l39 p166 m39 p170 n1 vss p1 p512 r1 vss t1 p502 u1 vss v1 p495 n2 p517 p2 p513 r2 p506 t2 p504 u2 p499 v2 p494 n3 p516 p3 p515 r3 p509 t3 p505 u3 p498 v3 p496 n4 p519 p4 p514 r4 p508 t4 p507 u4 p501 v4 p497 n5 p518 p5 v dd r5 p511 t5 v dd u5 p500 v5 v dd n6 p520 p6 v dd r6 p510 t6 v dd u6 p503 v6 v dd n34 p172 p34 v dd r34 p180 t34 v dd u34 p190 v34 v dd n35 p173 p35 v dd r35 p183 t35 v dd u35 p192 v35 v dd n36 p175 p36 p177 r36 p182 t36 p186 u36 p193 v36 p197 n37 p174 p37 p179 r37 p184 t37 p189 u37 p195 v37 p196 n38 p176 p38 p178 r38 p185 t38 p188 u38 p194 v38 p199 n39 vss p39 p181 r39 p187 t39 p191 u39 vss v39 p198 w1 p488 y1 p485 aa1 vss ab1 p479 ac1 p475 ad1 p468 w2 p489 y2 p484 aa2 p482 ab2 p476 ac2 p473 ad2 p466 w3 p491 y3 p486 aa3 p478 ab3 p477 ac3 p472 ad3 p467 w4 p490 y4 p487 aa4 p483 ab4 p474 ac4 p470 ad4 p465 w5 p492 y5 v dd aa5 p481 ab5 v dd ac5 p471 ad5 v dd w6 p493 y6 v dd aa6 p480 ab6 v dd ac6 p469 ad6 v dd w34 p200 y34 v dd aa34 p213 ab34 v dd ac34 p223 ad34 v dd w35 p201 y35 v dd aa35 p212 ab35 v dd ac35 p220 ad35 v dd w36 p203 y36 p206 aa36 p210 ab36 p217 ac36 p221 ad36 p227 w37 p202 y37 p207 aa37 p211 ab37 p216 ac37 p218 ad37 p225 w38 p205 y38 p204 aa38 p209 ab38 p214 ac38 p219 ad38 p224 w39 vss y39 p208 aa39 vss ab39 p215 ac39 vss ad39 p222 table 15 msx532 pinout by ball sequence (continued) ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name
msx family data sheet 36 [rev. 1.8] 2/28/01 i-cube, inc. ae1 vss af1 p458 ag1 p450 ah1 p451 aj1 p443 ak1 p441 ae2 p464 af2 p459 ag2 p454 ah2 p449 aj2 p447 ak2 p440 ae3 p462 af3 p457 ag3 p455 ah3 p448 aj3 p444 ak3 p438 ae4 p463 af4 p456 ag4 p452 ah4 p446 aj4 p445 ak4 p439 ae5 p460 af5 v dd ag5 p453 ah5 v dd aj5 p442 ak5 v dd ae6 p461 af6 v dd ag6 vss ah6 v dd aj6 vss ak6 v dd ae34 p230 af34 v dd ag34 p240 ah34 v dd aj34 p249 ak34 v dd ae35 p231 af35 v dd ag35 p238 ah35 v dd aj35 p248 ak35 v dd ae36 p228 af36 p234 ag36 p239 ah36 p245 aj36 p246 ak36 p253 ae37 p229 af37 p235 ag37 p236 ah37 p242 aj37 p247 ak37 p252 ae38 p226 af38 p233 ag38 p237 ah38 p243 aj38 p244 ak38 p250 ae39 vss af39 p232 ag39 vss ah39 p241 aj39 vss ak39 p251 al1 p433 am1 p432 an1 vss al2 p436 am2 p430 an2 p429 al3 p437 am3 p431 an3 p426 al4 p434 am4 p428 an4 p427 al5 p435 am5 vdd an5 p425 al6 vss am6 vdd an6 p423 al34 p258 am34 vdd an34 p271 al35 p259 am35 vdd an35 p268 al36 p257 am36 p262 an36 p269 al37 p256 am37 p263 an37 p267 al38 p254 am38 p260 an38 p264 al39 p255 am39 p261 an39 vss table 15 msx532 pinout by ball sequence (continued) ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 37 ap1 p424 ar1 vss at1 vss au1 vss av1 vss aw1 vss ap2 p422 ar2 p421 at2 oe_3# au2 vss av2 vss aw2 vss ap3 p420 ar3 p418 at3 vss au3 vss av3 vss aw3 vss ap4 p419 ar4 vss at4 vss au4 vss av4 clk_3 aw4 vss ap5 v dd ar5 vss at5 vss au5 p417 av5 p415 aw5 p410 ap6 v dd ar6 ie_3 at6 p416 au6 p414 av6 p412 aw6 p407 ap7 p413 ar7 p411 at7 p409 au7 p408 av7 p406 aw7 vss ap8 p404 ar8 p405 at8 p402 au8 p403 av8 p401 aw8 p400 ap9 p398 ar9 p399 at9 p396 au9 p397 av9 p394 aw9 vss ap10 v dd ar10 v dd at10 p395 au10 p393 av10 p392 aw10 p390 ap11 p391 ar11 p389 at11 p388 au11 p386 av11 vss aw11 p387 ap12 v dd ar12 v dd at12 p385 au12 p384 av12 p382 aw12 p383 ap13 p380 ar13 p381 at13 p378 au13 p379 av13 p377 aw13 vss ap14 v dd ar14 v dd at14 p376 au14 p374 av14 p375 aw14 p372 ap15 p373 ar15 p370 at15 p371 au15 p369 av15 p368 aw15 p366 ap16 v dd ar16 v dd at16 p367 au16 p364 av16 p365 aw16 p362 ap17 p363 ar17 p361 at17 p360 au17 p358 av17 p359 aw17 vss ap18 v dd ar18 v dd at18 p357 au18 p356 av18 p354 aw18 p355 ap19 p353 ar19 p352 at19 p350 au19 p351 av19 p348 aw19 vss ap20 v dd ar20 v dd at20 p346 au20 p347 av20 p349 aw20 p345 ap21 p341 ar21 p340 at21 p343 au21 p342 av21 p344 aw21 vss ap22 v dd ar22 v dd at22 p336 au22 p337 av22 p339 aw22 p338 ap23 p331 ar23 p330 at23 p332 au23 p333 av23 p335 aw23 p334 ap24 v dd ar24 v dd at24 p327 au24 p326 av24 p328 aw24 p329 ap25 p321 ar25 p323 at25 p322 au25 p325 av25 p324 aw25 vss ap26 v dd ar26 v dd at26 p316 au26 p319 av26 p318 aw26 p320 ap27 p310 ar27 p312 at27 p313 au27 p315 av27 p314 aw27 p317 ap28 v dd ar28 v dd at28 p306 au28 p309 av28 p308 aw28 p311 ap29 p303 ar29 p302 at29 p304 au29 p305 av29 p307 aw29 vss ap30 p296 ar30 p297 at30 p299 au30 p298 av30 p301 aw30 p300 ap31 p290 ar31 p293 at31 p292 au31 p295 av31 p294 aw31 vss ap32 v dd ar32 v dd at32 p286 au32 p289 av32 p288 aw32 p291 ap33 ie_2 ar33 p283 at33 p282 au33 p285 av33 p287 aw33 vss ap34 v dd ar34 p279 at34 p281 au34 p280 av34 oe_2# aw34 p284 ap35 v dd ar35 vss at35 vss au35 p276 av35 p278 aw35 clk_2 ap36 p274 ar36 vss at36 vss au36 vss av36 vss aw36 vss ap37 p272 ar37 p277 at37 vss au37 vss av37 vss aw37 vss ap38 p270 ar38 p273 at38 p275 au38 vss av38 vss aw38 vss ap39 p265 ar39 p266 at39 vss au39 vss av39 vss aw39 vss table 15 msx532 pinout by ball sequence (continued) ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name
msx family data sheet 38 [rev. 1.8] 2/28/01 i-cube, inc. 4.3 msx532 [792 tbga package] pinout: by ball name (alphabetically) l table 16 msx532 pinout by ball name ball name ball # ball name ball # ball name ball # ball name ball # ball name ball # clk_0 b4 p027 f13 p067 d21 p107 e29 p147 h36 clk_1 f37 p028 d13 p068 f21 p108 b30 p148 h38 clk_2 aw35 p029 e13 p069 e21 p109 a30 p149 h37 clk_3 av4 p030 c13 p070 b22 p110 d30 p150 j34 hw_rst# b5 p031 b13 p071 a22 p111 c30 p151 h39 ie_0 c5 p032 d14 p072 c22 p112 a31 p152 j35 ie_1 d38 p033 a13 p073 d22 p113 b31 p153 j36 ie_2 ap33 p034 b14 p074 b23 p114 d31 p154 j38 ie_3 ar6 p035 c14 p075 a23 p115 c31 p155 j37 oe_0# e6 p036 f15 p076 d23 p116 f31 p156 k35 oe_1# e38 p037 a14 p077 c23 p117 e31 p157 k34 oe_2# av34 p038 e15 p078 f23 p118 b32 p158 k37 oe_3# at2 p039 d15 p079 e23 p119 a32 p159 k36 p000 a6 p040 b15 p080 a24 p120 c32 p160 k38 p001 b6 p041 c15 p081 b24 p121 d32 p161 k39 p002 b7 p042 c16 p082 d24 p122 c33 p162 l35 p003 c7 p043 d16 p083 c24 p123 b33 p163 l34 p004 c8 p044 a16 p084 c25 p124 d33 p164 l37 p005 d8 p045 b16 p085 b25 p125 a34 p165 l36 p006 b8 p046 f17 p086 e25 p126 b34 p166 l39 p007 a8 p047 e17 p087 d25 p127 e33 p167 l38 p008 e9 p048 c17 p088 f25 p128 b35 p168 m36 p009 f9 p049 d17 p089 a26 p129 f33 p169 m37 p010 c9 p050 a17 p090 c26 p130 c34 p170 m39 p011 d9 p051 b17 p091 b26 p131 b36 p171 m38 p012 a9 p052 c18 p092 a27 p132 d34 p172 n34 p013 b9 p053 d18 p093 d26 p133 c35 p173 n35 p014 d10 p054 b18 p094 c27 p134 e37 p174 n37 p015 c10 p055 a18 p095 b27 p135 e34 p175 n36 p016 a10 p056 e19 p096 d27 p136 f36 p176 n38 p017 b10 p057 f19 p097 e27 p137 f35 p177 p36 p018 e11 p058 c19 p098 a28 p138 g34 p178 p38 p019 f11 p059 d19 p099 f27 p139 f38 p179 p37 p020 c11 p060 b20 p100 b28 p140 g36 p180 r34 p021 d11 p061 b19 p101 c28 p141 g35 p181 p39 p022 b11 p062 d20 p102 b29 p142 e39 p182 r36 p023 d12 p063 c20 p103 d28 p143 g37 p183 r35 p024 b12 p064 b21 p104 c29 p144 g38 p184 r37 p025 c12 p065 a20 p105 d29 p145 f39 p185 r38 p026 a12 p066 c21 p106 f29 p146 g39 p186 t36
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 39 p187 r39 p227 ad36 p267 an37 p307 av29 p347 au20 p188 t38 p228 ae36 p268 an35 p308 av28 p348 av19 p189 t37 p229 ae37 p269 an36 p309 au28 p349 av20 p190 u34 p230 ae34 p270 ap38 p310 ap27 p350 at19 p191 t39 p231 ae35 p271 an34 p311 aw28 p351 au19 p192 u35 p232 af39 p272 ap37 p312 ar27 p352 ar19 p193 u36 p233 af38 p273 ar38 p313 at27 p353 ap19 p194 u38 p234 af36 p274 ap36 p314 av27 p354 av18 p195 u37 p235 af37 p275 at38 p315 au27 p355 aw18 p196 v37 p236 ag37 p276 au35 p316 at26 p356 au18 p197 v36 p237 ag38 p277 ar37 p317 aw27 p357 at18 p198 v39 p238 ag35 p278 av35 p318 av26 p358 au17 p199 v38 p239 ag36 p279 ar34 p319 au26 p359 av17 p200 w34 p240 ag34 p280 au34 p320 aw26 p360 at17 p201 w35 p241 ah39 p281 at34 p321 ap25 p361 ar17 p202 w37 p242 ah37 p282 at33 p322 at25 p362 aw16 p203 w36 p243 ah38 p283 ar33 p323 ar25 p363 ap17 p204 y38 p244 aj38 p284 aw34 p324 av25 p364 au16 p205 w38 p245 ah36 p285 au33 p325 au25 p365 av16 p206 y36 p246 aj36 p286 at32 p326 au24 p366 aw15 p207 y37 p247 aj37 p287 av33 p327 at24 p367 at16 p208 y39 p248 aj35 p288 av32 p328 av24 p368 av15 p209 aa38 p249 aj34 p289 au32 p329 aw24 p369 au15 p210 aa36 p250 ak38 p290 ap31 p330 ar23 p370 ar15 p211 aa37 p251 ak39 p291 aw32 p331 ap23 p371 at15 p212 aa35 p252 ak37 p292 at31 p332 at23 p372 aw14 p213 aa34 p253 ak36 p293 ar31 p333 au23 p373 ap15 p214 ab38 p254 al38 p294 av31 p334 aw23 p374 au14 p215 ab39 p255 al39 p295 au31 p335 av23 p375 av14 p216 ab37 p256 al37 p296 ap30 p336 at22 p376 at14 p217 ab36 p257 al36 p297 ar30 p337 au22 p377 av13 p218 ac37 p258 al34 p298 au30 p338 aw22 p378 at13 p219 ac38 p259 al35 p299 at30 p339 av22 p379 au13 p220 ac35 p260 am38 p300 aw30 p340 ar21 p380 ap13 p221 ac36 p261 am39 p301 av30 p341 ap21 p381 ar13 p222 ad39 p262 am36 p302 ar29 p342 au21 p382 av12 p223 ac34 p263 am37 p303 ap29 p343 at21 p383 aw12 p224 ad38 p264 an38 p304 at29 p344 av21 p384 au12 p225 ad37 p265 ap39 p305 au29 p345 aw20 p385 at12 p226 ae38 p266 ar39 p306 at28 p346 at20 p386 au11 table 16 msx532 pinout by ball name (continued) ball name ball # ball name ball # ball name ball # ball name ball # ball name ball #
msx family data sheet 40 [rev. 1.8] 2/28/01 i-cube, inc. p387 aw11 p427 an4 p467 ad3 p507 t4 rcb3 g2 p388 at11 p428 am4 p468 ad1 p508 r4 rcb4 h4 p389 ar11 p429 an2 p469 ac6 p509 r3 rcb5 h3 p390 aw10 p430 am2 p470 ac4 p510 r6 rcb6 h2 p391 ap11 p431 am3 p471 ac5 p511 r5 rcb7 h1 p392 av10 p432 am1 p472 ac3 p512 p1 rcb8 j6 p393 au10 p433 al1 p473 ac2 p513 p2 rcb9 j5 p394 av9 p434 al4 p474 ab4 p514 p4 rcc0 j4 p395 at10 p435 al5 p475 ac1 p515 p3 rcc1 j3 p396 at9 p436 al2 p476 ab2 p516 n3 rcc2 j2 p397 au9 p437 al3 p477 ab3 p517 n2 rcc3 k6 p398 ap9 p438 ak3 p478 aa3 p518 n5 rce k1 p399 ar9 p439 ak4 p479 ab1 p519 n4 rci0 k5 p400 aw8 p440 ak2 p480 aa6 p520 n6 rci1 k4 p401 av8 p441 ak1 p481 aa5 p521 m1 rc_rdy d6 p402 at8 p442 aj5 p482 aa2 p522 m3 tck d7 p403 au8 p443 aj1 p483 aa4 p523 m2 tdi f7 p404 ap8 p444 aj3 p484 y2 p524 m4 tdo e7 p405 ar8 p445 aj4 p485 y1 p525 m5 tms c6 p406 av7 p446 ah4 p486 y3 p526 l1 trst# a5 p407 aw6 p447 aj2 p487 y4 p527 m6 update l6 p408 au7 p448 ah3 p488 w1 p528 l2 v dd e8 p409 at7 p449 ah2 p489 w2 p529 l3 v dd e10 p410 aw5 p450 ag1 p490 w4 p530 l5 v dd e12 p411 ar7 p451 ah1 p491 w3 p531 l4 v dd e14 p412 av6 p452 ag4 p492 w5 rc_clk k3 v dd e16 p413 ap7 p453 ag5 p493 w6 rc_en# k2 v dd e18 p414 au6 p454 ag2 p494 v2 rca0 e3 v dd e20 p415 av5 p455 ag3 p495 v1 rca1 d2 v dd e22 p416 at6 p456 af4 p496 v3 rca2 f5 v dd e24 p417 au5 p457 af3 p497 v4 rca3 e2 v dd e26 p418 ar3 p458 af1 p498 u3 rca4 f4 v dd e28 p419 ap4 p459 af2 p499 u2 rca5 f3 v dd e30 p420 ap3 p460 ae5 p500 u5 rca6 e1 v dd e32 p421 ar2 p461 ae6 p501 u4 rca7 g6 v dd f6 p422 ap2 p462 ae3 p502 t1 rca8 f2 v dd f8 p423 an6 p463 ae4 p503 u6 rca9 g5 v dd f10 p424 ap1 p464 ae2 p504 t2 rcb0 g4 v dd f12 p425 an5 p465 ad4 p505 t3 rcb1 f1 v dd f14 p426 an3 p466 ad2 p506 r2 rcb2 g3 v dd f16 table 16 msx532 pinout by ball name (continued) ball name ball # ball name ball # ball name ball # ball name ball # ball name ball #
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 41 v dd f18 v dd af6 v dd ar32 v ss e4 v ss au3 v dd f20 v dd af34 v ss a1 v ss e5 v ss au4 v dd f22 v dd af35 v ss a2 v ss e35 v ss au36 v dd f24 v dd ah5 v ss a3 v ss e36 v ss au37 v dd f26 v dd ah6 v ss a4 v ss g1 v ss au38 v dd f28 v dd ah34 v ss a7 v ss j1 v ss au39 v dd f30 v dd ah35 v ss a11 v ss j39 v ss av 1 v dd f32 v dd ak5 v ss a15 v ss n1 v ss av 2 v dd f34 v dd ak6 v ss a19 v ss n39 v ss av 3 v dd h5 v dd ak34 v ss a21 v ss r1 v ss av 11 v dd h6 v dd ak35 v ss a25 v ss u1 v ss av 3 6 v dd h34 v dd am5 v ss a29 v ss u39 v ss av 3 7 v dd h35 v dd am6 v ss a33 v ss w39 v ss av 3 8 v dd m34 v dd am34 v ss a35 v ss aa1 v ss av 3 9 v dd m35 v dd am35 v ss a36 v ss aa39 v ss aw1 v dd p5 v dd ap5 v ss a37 v ss ac39 v ss aw2 v dd p6 v dd ap6 v ss a38 v ss ae1 v ss aw3 v dd p34 v dd ap10 v ss a39 v ss ae39 v ss aw4 v dd p35 v dd ap12 v ss b1 v ss ag6 v ss aw7 v dd t5 v dd ap14 v ss b2 v ss ag39 v ss aw9 v dd t6 v dd ap16 v ss b3 v ss aj6 v ss aw13 v dd t34 v dd ap18 v ss b37 v ss aj39 v ss aw17 v dd t35 v dd ap20 v ss b38 v ss al6 v ss aw19 v dd v5 v dd ap22 v ss b39 v ss an1 v ss aw21 v dd v6 v dd ap24 v ss c1 v ss an39 v ss aw25 v dd v34 v dd ap26 v ss c2 v ss ar1 v ss aw29 v dd v35 v dd ap28 v ss c3 v ss ar4 v ss aw31 v dd y5 v dd ap32 v ss c4 v ss ar5 v ss aw33 v dd y6 v dd ap34 v ss c36 v ss ar35 v ss aw36 v dd y34 v dd ap35 v ss c37 v ss ar36 v ss aw37 v dd y35 v dd ar10 v ss c38 v ss at 1 v ss aw38 v dd ab5 v dd ar12 v ss c39 v ss at 3 v ss aw39 v dd ab6 v dd ar14 v ss d1 v ss at 4 v dd ab34 v dd ar16 v ss d3 v ss at 5 v dd ab35 v dd ar18 v ss d4 v ss at 3 5 v dd ad5 v dd ar20 v ss d5 v ss at 3 6 v dd ad6 v dd ar22 v ss d35 v ss at 3 7 v dd ad34 v dd ar24 v ss d36 v ss at 3 9 v dd ad35 v dd ar26 v ss d37 v ss au1 v dd af5 v dd ar28 v ss d39 v ss au2 table 16 msx532 pinout by ball name (continued) ball name ball # ball name ball # ball name ball # ball name ball # ball name ball #
msx family data sheet 42 [rev. 1.8] 2/28/01 i-cube, inc. 4.4 msx340 [480 pbga package] pinout c d e f g h j k l m n p r t u v w y aa ab ac ad clk_3 oe_3# p276 p290 p175 p087 p091 ie_1 p304 rci0 rcb3 p330 p310 p164 p170 p173 p171 p174 p176 p183 clk_2 p166 p167 p158 p161 p182 p187 p141 p143 p140 p145 p146 p144 p152 p153 p150 p156 p157 p154 p160 p123 p121 p125 p124 p126 p129 p130 p136 p139 p137 p116 p117 p114 p113 p093 p094 p098 p108 p102 p110 p112 p106 p103 p099 clk_1 p092 p095 p086 p083 p076 p079 p082 p072 p073 p066 c d e f g h j k l m n p r t u v w y aa ab ac ad 1234567891011121314151617181920212223242526 p188 p198 p192 p191 ie_2 p190 p221 p223 p196 p215 p214 p216 p210 p212 p213 p206 p204 p200 p208 p207 p199 p197 p205 p201 p068 p064 p056 p065 p057 p060 p058 p055 p048 p046 p049 p047 p042 p037 p027 p026 p029 p023 p025 p024 p018 p017 p021 p014 p019 p013 p009 p032 p053 p041 p036 p039 p078 p034 p031 p069 p035 p043 p059 p062 p075 p222 p273 p277 p281 p322 p321 p283 p261 p266 p270 p267 p309 p263 p256 p250 p257 p254 p260 p253 p252 p246 p247 p248 p230 p245 p236 p234 p237 p235 p243 p240 p244 p228 p225 p218 p227 p232 p224 p293 p316 p318 p300 p297 p298 p296 p317 p313 p312 p289 p284 p287 p305 p295 p301 p003 p010 p015 p012 p004 tdo p000 p008 oe_0# tms p326 rca2 rcc0 rcb2 rcb0 rcb6 rcb5 rca7 rca6 rca8 p336 rc_en# rc_clk rca3 p005 rca4 p332 p337 p338 p328 p329 p333 rce rcc3 rcc2 msx340 in 480 pbga top view p279 rc_rdy p070 p054 p052 p045 p033 p028 p020 p050 p038 p016 p006 hw_rst# p067 p063 p044 p040 p030 p022 p051 p061 p011 p007 b p186 b p195 p220 p217 p209 p202 p269 p241 p229 p238 p242 p226 v ss p181 a p193 a p203 p194 v dd p219 p211 p262 p249 p251 p231 p233 p239 p179 oe_1# p169 p172 p163 p142 p148 p155 p159 p131 p128 p132 p138 p122 p118 p100 p105 p107 p109 p111 p096 p089 p085 p177 p080 p074 p185 p184 p275 p274 rca1 p299 p320 rci1 rcb4 p331 p307 p282 p265 p268 ie_3 p272 p324 p271 p306 p303 p319 p315 p286 p294 p288 p314 p311 p308 p278 p285 p280 p302 p292 p291 p325 ie_0 rca0 rcc1 rcb7 rcb9 rcb8 rcb1 rca9 p335 p334 tdi clk_0 rca5 p327 p323 p339 update tck p001 trst# p002 p258 p264 p255 p259 ae af ag ah aj ae af ag ah aj 27 28 29 1234567891011121314151617181920212223242526272829 oe_2# p189 p180 p178 p168 p165 p162 p147 p149 p151 p127 p133 p134 p135 p120 p115 p119 p097 p101 p104 p090 p084 p088 p081 p077 p071 v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 43 4.5 msx340 [480 pbga package] pinout: by ball sequence table 17 msx340 pinout by ball sequence ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name a1 v ss b1 v ss c1 v ss d1 v dd e1 p174 a2 p181 b2 v ss c2 v ss d2 v dd e2 p176 a3 p184 b3 p185 c3 v dd d3 v dd e3 p179 a4 oe_2# b4 p189 c4 p180 d4 p177 e4 p178 a5 p193 b5 p186 c5 clk_2 d5 p183 e5 p175 a6 p194 b6 p195 c6 p190 d6 ie_2 e6 p182 a7 v dd b7 v ss c7 p196 d7 p188 e7 p187 a8 p203 b8 v ss c8 p198 d8 p192 e8 p191 a9 v dd b9 p202 c9 p201 d9 p199 e9 p197 a10 v dd b10 v ss c10 p205 d10 p204 e10 p200 a11 p211 b11 p209 c11 p208 d11 p207 e11 p206 a12 v dd b12 v ss c12 p213 d12 p212 e12 p210 a13 p219 b13 p217 c13 p216 d13 p214 e13 p215 a14 v dd b14 p220 c14 p223 d14 p221 e14 p218 a15 v dd b15 v ss c15 p222 d15 p224 e15 p225 a16 v dd b16 p226 c16 p228 d16 p227 e16 p232 a17 p231 b17 p229 c17 p230 d17 p235 e17 p237 a18 p233 b18 v ss c18 p234 d18 p236 e18 p243 a19 p239 b19 p238 c19 p240 d19 p245 e19 p248 a20 v dd b20 p241 c20 p247 d20 p246 e20 p252 a21 v dd b21 p242 c21 p244 d21 p253 e21 p257 a22 p249 b22 v ss c22 p250 d22 p256 e22 p263 a23 p251 b23 v ss c23 p254 d23 p260 e23 p266 a24 v dd b24 v ss c24 p261 d24 p267 e24 p270 a25 p255 b25 p258 c25 p265 d25 p271 e25 ie_3 a26 p259 b26 p264 c26 p268 d26 p272 e26 p275 a27 p262 b27 p269 c27 p273 d27 oe_3# e27 p279 a28 v dd b28 v ss c28 clk_3 d28 p276 e28 p281 a29 v ss b29 v ss c29 p277 d29 v dd e29 p283
msx family data sheet 44 [rev. 1.8] 2/28/01 i-cube, inc. f1 p170 g1 p167 h1 p160 j1 p156 k1 p152 f2 p173 g2 p166 h2 p161 j2 p157 k2 p153 f3 p172 g3 p169 h3 p163 j3 p159 k3 p155 f4 p168 g4 p165 h4 p162 j4 v dd k4 p151 f5 p171 g5 p164 h5 p158 j5 p154 k5 p150 f25 p274 g25 p278 h25 p282 j25 p286 k25 p292 f26 p280 g26 p285 h26 p288 j26 p294 k26 p291 f27 p284 g27 p289 h27 p296 j27 p297 k27 p293 f28 p287 g28 v ss h28 v ss j28 p298 k28 p300 f29 p290 g29 v dd h29 v dd j29 v dd k29 p301 l1 p145 m1 p141 n1 p137 p1 v dd r1 v dd l2 p146 m2 p143 n2 p139 p2 p130 r2 p126 l3 p148 m3 p142 n3 p138 p3 p132 r3 p128 l4 p149 m4 p147 n4 p135 p4 p134 r4 p133 l5 p144 m5 p140 n5 p136 p5 p129 r5 p124 l25 p299 m25 p303 n25 p307 p25 p311 r25 p315 l26 p302 m26 p306 n26 p308 p26 p314 r26 p319 l27 p295 m27 p309 n27 p312 p27 p317 r27 p318 l28 v ss m28 p305 n28 v ss p28 p313 r28 p316 l29 p304 m29 v dd n29 p310 p29 v dd r29 v dd t1 v dd u1 p123 v1 v dd w1 p114 y1 p112 t2 p125 u2 v ss v2 p117 w2 v ss y2 p110 t3 p131 u3 p122 v3 p118 w3 p111 y3 p109 t4 p127 u4 p120 v4 p119 w4 p115 y4 v dd t5 p121 u5 p116 v5 p113 w5 p106 y5 p102 t25 p320 u25 p325 v25 p331 w25 p334 y25 update t26 p324 u26 p323 v26 p327 w26 p335 y26 p339 t27 p322 u27 p329 v27 p332 w27 p338 y27 rc_clk t28 p321 u28 p328 v28 p333 w28 p337 y28 rc_en# t29 v dd u29 p326 v29 p330 w29 p336 y29 rce aa1 v ss ab1 v ss ac1 v ss ad1 p103 aa2 p108 ab2 v ss ac2 v ss ad2 p099 aa3 p107 ab3 p105 ac3 p100 ad3 p096 aa4 p104 ab4 p101 ac4 p097 ad4 p090 aa5 p098 ab5 p094 ac5 p093 ad5 clk1 aa25 rci1 ab25 rcc1 ac25 rcb4 ad25 rca9 aa26 rcb9 ab26 rcb8 ac26 rcb7 ad26 rcb1 aa27 rcc2 ab27 rcb5 ac27 rcb0 ad27 rca6 aa28 rcc3 ab28 rcb6 ac28 rcb2 ad28 rca7 aa29 rci0 ab29 rcc0 ac29 rcb3 ad29 rca8 table 17 msx340 pinout by ball sequence (continued) ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 45 ae1 p095 af1 v dd ag1 ie_1 ah1 v ss aj1 v ss ae2 p092 af2 p091 ag2 p086 ah2 v ss aj2 v dd ae3 oe_1# af3 p089 ag3 p085 ah3 p080 aj3 p074 ae4 p088 af4 p084 ag4 p081 ah4 p077 aj4 p071 ae5 p087 af5 p083 ag5 p076 ah5 p070 aj5 p067 ae6 p082 af6 p079 ag6 p072 ah6 v ss aj6 v dd ae7 p078 af7 p073 ag7 p066 ah7 v ss aj7 p063 ae8 p075 af8 p069 ag8 p062 ah8 v ss aj8 p061 ae9 p068 af9 p064 ag9 p056 ah9 p054 aj9 v dd ae10 p065 af10 p057 ag10 p060 ah10 p052 aj10 v dd ae11 p058 af11 p059 ag11 p053 ah11 p050 aj11 p051 ae12 p055 af12 p048 ag12 p046 ah12 v ss aj12 p044 ae13 p049 af13 p047 ag13 p042 ah13 p045 aj13 p040 ae14 p043 af14 p041 ag14 p039 ah14 p038 aj14 v dd ae15 p036 af15 p034 ag15 p032 ah15 v ss aj15 v dd ae16 p031 af16 p035 ag16 p037 ah16 p033 aj16 v dd ae17 p027 af17 p026 ag17 p029 ah17 p028 aj17 p030 ae18 p023 af18 p025 ag18 p024 ah18 v ss aj18 v dd ae19 p018 af19 p017 ag19 p021 ah19 p020 aj19 p022 ae20 p014 af20 p019 ag20 p013 ah20 v ss aj20 v dd ae21 p009 af21 p010 ag21 p015 ah21 p016 aj21 v dd ae22 p003 af22 p004 ag22 p012 ah22 v ss aj22 p011 ae23 tdo af23 p000 ag23 p008 ah23 v ss aj23 v dd ae24 oe_0# af24 tms ag24 p005 ah24 p006 aj24 p007 ae25 rca5 af25 clk_0 ag25 tdi ah25 p001 aj25 p002 ae26 rca1 af26 rca0 ag26 ie_0 ah26 tck aj26 trst# ae27 rca2 af27 v ss ag27 v ss ah27 rc_rdy aj27 hw_rst# ae28 rca4 af28 v dd ag28 v ss ah28 v ss aj28 v ss ae29 rca3 af29 v dd ag29 v ss ah29 v ss aj29 v ss table 17 msx340 pinout by ball sequence (continued) ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name
msx family data sheet 46 [rev. 1.8] 2/28/01 i-cube, inc. 4.6 msx340 [480 pbga package] pinout: by ball name table 18 msx340 pinout by ball name ball name ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name ball # clk_0 af25 p031 ae16 p075 ae8 p119 v4 p163 h3 p207 d11 clk_1 ad5 p032 ag15 p076 ag5 p120 u4 p164 g5 p208 c11 clk_2 c5 p033 ah16 p077 ah4 p121 t5 p165 g4 p209 b11 clk_3 c28 p034 af15 p078 ae7 p122 u3 p166 g2 p210 e12 hw_rst# aj27 p035 af16 p079 af6 p123 u1 p167 g1 p211 a11 ie_0 ag26 p036 ae15 p080 ah3 p124 r5 p168 f4 p212 d12 ie_1 ag1 p037 ag16 p081 ag4 p125 t2 p169 g3 p213 c12 ie_2 d6 p038 ah14 p082 ae6 p126 r2 p170 f1 p214 d13 ie_3 e25 p039 ag14 p083 af5 p127 t4 p171 f5 p215 e13 oe_0# ae24 p040 aj13 p084 af4 p128 r3 p172 f3 p216 c13 oe_1# ae3 p041 af14 p085 ag3 p129 p5 p173 f2 p217 b13 oe_2# a4 p042 ag13 p086 ag2 p130 p2 p174 e1 p218 e14 oe_3# d27 p043 ae14 p087 ae5 p131 t3 p175 e5 p219 a13 p000 af23 p044 aj12 p088 ae4 p132 p3 p176 e2 p220 b14 p001 ah25 p045 ah13 p089 af3 p133 r4 p177 d4 p221 d14 p002 aj25 p046 ag12 p090 ad4 p134 p4 p178 e4 p222 c15 p003 ae22 p047 af13 p091 af2 p135 n4 p179 e3 p223 c14 p004 af22 p048 af12 p092 ae2 p136 n5 p180 c4 p224 d15 p005 ag24 p049 ae13 p093 ac5 p137 n1 p181 a2 p225 e15 p006 ah24 p050 ah11 p094 ab5 p138 n3 p182 e6 p226 b16 p007 aj24 p051 aj11 p095 ae1 p139 n2 p183 d5 p227 d16 p008 ag23 p052 ah10 p096 ad3 p140 m5 p184 a3 p228 c16 p009 ae21 p053 ag11 p097 ac4 p141 m1 p185 b3 p229 b17 p010 af21 p054 ah9 p098 aa5 p142 m3 p186 b5 p230 c17 p011 aj22 p055 ae12 p099 ad2 p143 m2 p187 e7 p231 a17 p012 ag22 p056 ag9 p100 ac3 p144 l5 p188 d7 p232 e16 p013 ag20 p057 af10 p101 ab4 p145 l1 p189 b4 p233 a18 p014 ae20 p058 ae11 p102 y5 p146 l2 p190 c6 p234 c18 p015 ag21 p059 af11 p103 ad1 p147 m4 p191 e8 p235 d17 p016 ah21 p060 ag10 p104 aa4 p148 l3 p192 d8 p236 d18 p017 af19 p061 aj8 p105 ab3 p149 l4 p193 a5 p237 e17 p018 ae19 p062 ag8 p106 w5 p150 k5 p194 a6 p238 b19 p019 af20 p063 aj7 p107 aa3 p151 k4 p195 b6 p239 a19 p020 ah19 p064 af9 p108 aa2 p152 k1 p196 c7 p240 c19 p021 ag19 p065 ae10 p109 y3 p153 k2 p197 e9 p241 b20 p022 aj19 p066 ag7 p110 y2 p154 j5 p198 c8 p242 b21 p023 ae18 p067 aj5 p111 w3 p155 k3 p199 d9 p243 e18 p024 ag18 p068 ae9 p112 y1 p156 j1 p200 e10 p244 c21 p025 af18 p069 af8 p113 v5 p157 j2 p201 c9 p245 d19 p026 af17 p070 ah5 p114 w1 p158 h5 p202 b9 p246 d20 p027 ae17 p071 aj4 p115 w4 p159 j3 p203 a8 p247 c20 p028 ah17 p072 ag6 p116 u5 p160 h1 p204 d10 p248 e19 p029 ag17 p073 af7 p117 v2 p161 h2 p205 c10 p249 a22 p030 aj17 p074 aj3 p118 v3 p162 h4 p206 e11 p250 c22
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 47 p251 a23 p295 l27 p339 y26 v dd a20 v ss ag27 p252 e20 p296 h27 rc_en# y28 v dd a21 v ss ag28 p253 d21 p297 j27 rc_clk y27 v dd a24 v ss ag29 p254 c23 p298 j28 rca0 af26 v dd a28 v ss ah1 p255 a25 p299 l25 rca1 ae26 v dd af1 v ss ah2 p256 d22 p300 k28 rca2 ae27 v dd af28 v ss ah6 p257 e21 p301 k29 rca3 ae29 v dd af29 v ss ah7 p258 b25 p302 l26 rca4 ae28 v dd aj2 v ss ah8 p259 a26 p303 m25 rca5 ae25 v dd aj6 v ss ah12 p260 d23 p304 l29 rca6 ad27 v dd aj9 v ss ah15 p261 c24 p305 m28 rca7 ad28 v dd aj10 v ss ah18 p262 a27 p306 m26 rca8 ad29 v dd aj14 v ss ah20 p263 e22 p307 n25 rca9 ad25 v dd aj15 v ss ah22 p264 b26 p308 n26 rcb0 ac27 v dd aj16 v ss ah23 p265 c25 p309 m27 rcb1 ad26 v dd aj18 v ss ah28 p266 e23 p310 n29 rcb2 ac28 v dd aj20 v ss ah29 p267 d24 p311 p25 rcb3 ac29 v dd aj21 v ss aj1 p268 c26 p312 n27 rcb4 ac25 v dd aj23 v ss aj28 p269 b27 p313 p28 rcb5 ab27 v dd c3 v ss aj29 p270 e24 p314 p26 rcb6 ab28 v dd d1 v ss b1 p271 d25 p315 r25 rcb7 ac26 v dd d2 v ss b2 p272 d26 p316 r28 rcb8 ab26 v dd d3 v ss b7 p273 c27 p317 p27 rcb9 aa26 v dd d29 v ss b8 p274 f25 p318 r27 rcc0 ab29 v dd g29 v ss b10 p275 e26 p319 r26 rcc1 ab25 v dd h29 v ss b12 p276 d28 p320 t25 rcc2 aa27 v dd j4 v ss b15 p277 c29 p321 t28 rcc3 aa28 v dd j29 v ss b18 p278 g25 p322 t27 rce y29 v dd m29 v ss b22 p279 e27 p323 u26 rci0 aa29 v dd p1 v ss b23 p280 f26 p324 t26 rci1 aa25 v dd p29 v ss b24 p281 e28 p325 u25 rc_rdy ah27 v dd r1 v ss b28 p282 h25 p326 u29 trst# aj26 v dd r29 v ss b29 p283 e29 p327 v26 tck ah26 v dd t1 v ss c1 p284 f27 p328 u28 tdi ag25 v dd t29 v ss c2 p285 g26 p329 u27 tdo ae23 v dd v1 v ss g28 p286 j25 p330 v29 tms af24 v dd y4 v ss h28 p287 f28 p331 v25 update y25 v ss a1 v ss l28 p288 h26 p332 v27 v dd a7 v ss a29 v ss n28 p289 g27 p333 v28 v dd a9 v ss aa1 v ss u2 p290 f29 p334 w25 v dd a10 v ss ab1 v ss w2 p291 k26 p335 w26 v dd a12 v ss ab2 p292 k25 p336 w29 v dd a14 v ss ac1 p293 k27 p337 w28 v dd a15 v ss ac2 p294 j26 p338 w27 v dd a16 v ss af27 table 18 msx340 pinout by ball name (continued) ball name ball # ball name ball # ball name ball # ball name ball # ball name ball # ball name ball #
msx family data sheet 48 [rev. 1.8] 2/28/01 i-cube, inc. 4.7 792 tbga package dimensions (bottom view)
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 49 4.8 792 tbga package dimensions (top and side view)
msx family data sheet 50 [rev. 1.8] 2/28/01 i-cube, inc. 4.9 480 pbga package dimensions (bottom view)
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 51 4.10 480 pbga package dimensions (top and side view)
msx family data sheet 52 [rev. 1.8] 2/28/01 i-cube, inc. 4.11 port cross-reference for the msx532 and msx340 table 19 port cross-reference for msx532 and msx340 msx532 port # msx340 port # msx532 port # msx340 port # msx532 port # msx340 port # msx532 port # msx340 port # msx532 port # msx340 port # p000 p000 p040 p016 p080 p056 p120 p072 p160 ? p001 p001 p041 p017 p081 p057 p121 p073 p161 ? p002 p002 p042 p018 p082 p058 p122 p074 p162 ? p003 p003 p043 p019 p083 p059 p123 p075 p163 ? p004 p004 p044 p020 p084 p060 p124 p076 p164 ? p005 p005 p045 p021 p085 ? p125 p077 p165 ? p006 p006 p046 p022 p086 ? p126 p078 p166 ? p007 p007 p047 p023 p087 ? p127 p079 p167 ? p008 p008 p048 p024 p088 ? p128 p080 p168 ? p009 p009 p049 p025 p089 ? p129 p081 p169 ? p010 ? p050 p026 p090 ? p130 p082 p170 ? p011 ? p051 p027 p091 ? p131 p083 p171 ? p012 ? p052 p028 p092 ? p132 p084 p172 ? p013 ? p053 p029 p093 ? p133 p085 p173 ? p014 ? p054 p030 p094 ? p134 p086 p174 ? p015 ? p055 p031 p095 ? p135 p087 p175 ? p016 ? p056 p032 p096 ? p136 p088 p176 p104 p017 ? p057 p033 p097 ? p137 p089 p177 p105 p018 ? p058 p034 p098 ? p138 p090 p178 p106 p019 ? p059 p035 p099 ? p139 p091 p179 p107 p020 ? p060 p036 p100 ? p140 p092 p180 p108 p021 ? p061 p037 p101 ? p141 p093 p181 p109 p022 ? p062 p038 p102 ? p142 p094 p182 p110 p023 ? p063 p039 p103 ? p143 p095 p183 p111 p024 ? p064 p040 p104 ? p144 p096 p184 p112 p025 ? p065 p041 p105 ? p145 p097 p185 p113 p026 ? p066 p042 p106 ? p146 p098 p186 p114 p027 ? p067 p043 p107 ? p147 p099 p187 p115 p028 ? p068 p044 p108 ? p148 p100 p188 p116 p029 ? p069 p045 p109 p061 p149 p101 p189 p117 p030 ? p070 p046 p110 p062 p150 p102 p190 p118 p031 ? p071 p047 p111 p063 p151 p103 p191 p119 p032 ? p072 p048 p112 p064 p152 ? p192 p120 p033 ? p073 p049 p113 p065 p153 ? p193 p121 p034 p010 p074 p050 p114 p066 p154 ? p194 p122 p035 p011 p075 p051 p115 p067 p155 ? p195 p123 p036 p012 p076 p052 p116 p068 p156 ? p196 p124 p037 p013 p077 p053 p117 p069 p157 ? p197 p125 p038 p014 p078 p054 p118 p070 p158 ? p198 p126 p039 p015 p079 p055 p119 p071 p159 ? p199 p127
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 53 p200 p128 p240 ? p280 p184 p320 p200 p360 p240 p201 p129 p241 ? p281 p185 p321 p201 p361 p241 p202 p130 p242 ? p282 p186 p322 p202 p362 p242 p203 p131 p243 ? p283 p187 p323 p203 p363 p243 p204 p132 p244 ? p284 p188 p324 p204 p364 p244 p205 p133 p245 ? p285 p189 p325 p205 p365 p245 p206 p134 p246 ? p286 p190 p326 p206 p366 p246 p207 p135 p247 ? p287 p191 p327 p207 p367 p247 p208 p136 p248 ? p288 p192 p328 p208 p368 p248 p209 p137 p249 ? p289 p193 p329 p209 p369 ? p210 p138 p250 ? p290 p194 p330 p210 p370 ? p211 p139 p251 ? p291 p195 p331 p211 p371 ? p212 p140 p252 p156 p292 p196 p332 p212 p372 ? p213 p141 p253 p157 p293 p197 p333 p213 p373 ? p214 p142 p254 p158 p294 ? p334 p214 p374 ? p215 p143 p255 p159 p295 ? p335 p215 p375 ? p216 p144 p256 p160 p296 ? p336 p216 p376 ? p217 p145 p257 p161 p297 ? p337 p217 p377 ? p218 p146 p258 p162 p298 ? p338 p218 p378 ? p219 p147 p259 p163 p299 ? p339 p219 p379 ? p220 p148 p260 p164 p300 ? p340 p220 p380 ? p221 p149 p261 p165 p301 ? p341 p221 p381 ? p222 p150 p262 p166 p302 ? p342 p222 p382 ? p223 p151 p263 p167 p303 ? p343 p223 p383 ? p224 p152 p264 p168 p304 ? p344 p224 p384 ? p225 p153 p265 p169 p305 ? p345 p225 p385 ? p226 p154 p266 p170 p306 ? p346 p226 p386 ? p227 p155 p267 p171 p307 ? p347 p227 p387 ? p228 ? p268 p172 p308 ? p348 p228 p388 ? p229 ? p269 p173 p309 ? p349 p229 p389 ? p230 ? p270 p174 p310 ? p350 p230 p390 ? p231 ? p271 p175 p311 ? p351 p231 p391 ? p232 ? p272 p176 p312 ? p352 p232 p392 ? p233 ? p273 p177 p313 ? p353 p233 p393 p249 p234 ? p274 p178 p314 ? p354 p234 p394 p250 p235 ? p275 p179 p315 ? p355 p235 p395 p251 p236 ? p276 p180 p316 ? p356 p236 p396 p252 p237 ? p277 p181 p317 ? p357 p237 p397 p253 p238 ? p278 p182 p318 p198 p358 p238 p398 p254 p239 ? p279 p183 p319 p199 p359 p239 p399 p255 table 19 port cross-reference for msx532 and msx340 (continued) msx532 port # msx340 port # msx532 port # msx340 port # msx532 port # msx340 port # msx532 port # msx340 port # msx532 port # msx340 port #
msx family data sheet 54 [rev. 1.8] 2/28/01 i-cube, inc. p400 p256 p440 p296 p480 p312 p520 ? p401 p257 p441 p297 p481 p313 p521 ? p402 p258 p442 p298 p482 p314 p522 ? p403 p259 p443 p299 p483 p315 p523 ? p404 p260 p444 p300 p484 p316 p524 ? p405 p261 p445 p301 p485 p317 p525 ? p406 p262 p446 ? p486 p318 p526 ? p407 p263 p447 ? p487 p319 p527 ? p408 p264 p448 ? p488 p320 p528 ? p409 p265 p449 ? p489 p321 p529 ? p410 p266 p450 ? p490 p322 p530 ? p411 p267 p451 ? p491 p323 p531 ? p412 p268 p452 ? p492 p324 p413 p269 p453 ? p493 p325 p414 p270 p454 ? p494 p326 p415 p271 p455 ? p495 p327 p416 p272 p456 ? p496 p328 p417 p273 p457 ? p497 p329 p418 p274 p458 ? p498 p330 p419 p275 p459 ? p499 p331 p420 p276 p460 ? p500 p332 p421 p277 p461 ? p501 p333 p422 p278 p462 ? p502 p334 p423 p279 p463 ? p503 p335 p424 p280 p464 ? p504 p336 p425 p281 p465 ? p505 p337 p426 p282 p466 ? p506 p338 p427 p283 p467 ? p507 p339 p428 p284 p468 ? p508 ? p429 p285 p469 ? p509 ? p430 p286 p470 p302 p510 ? p431 p287 p471 p303 p511 ? p432 p288 p472 p304 p512 ? p433 p289 p473 p305 p513 ? p434 p290 p474 p306 p514 ? p435 p291 p475 p307 p515 ? p436 p292 p476 p308 p516 ? p437 p293 p477 p309 p517 ? p438 p294 p478 p310 p518 ? p439 p295 p479 p311 p519 ? table 19 port cross-reference for msx532 and msx340 (continued) msx532 port # msx340 port # msx532 port # msx340 port # msx532 port # msx340 port # msx532 port # msx340 port # msx532 port # msx340 port #
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 55 4.12 package thermal characteristics note ? thermal performance values are based on simulation data. table 20 package thermal characteristics package pin count jc ( c/w) ja ( c/w) still air ja ( c/w) 200 lfpm ja ( c/w) 300 lfpm ja ( c/w) 500 lfpm tbga 792 0.4 7.58 6.00 5.66 5.26 pbga 480 1.7 12.2 10.6 9.86 na
msx family data sheet 56 [rev. 1.8] 2/28/01 i-cube, inc. 5. power consumption there are three components to consider when calculating power for the msx family of devices: 1. steady state component ? this element equals 252 milliwatts. 2. connection component ? this element equals .006mw x mb/s x connections. 3. ouput drive component ? this element equals .013mw x number of outputs x mb/s x capacative load (pf). power consumption = steady state component + connection component + ouput drive component . = 252mw + (0.006 x mb/s x #connections) + (0.013 x mb/s x #outputs x cload) the following examples shows the total power consumption as determined by the above formula: example 1 100 mb/s into a 10pf load with 266 inputs connected to 266 outputs: power consumption = 252 mwatts + (0.006 x 100 x 266) + (0.013 x 266 x 100 x 10) = 252mw + 159.6mw + 3458mw = 3.87 watts example 2 300 mb/s into a 10pf load with 266 inputs connected to 266 outputs: power consumption = 252 mwatts + (0.006 x 300 x 266) + (0.013 x 266 x 300 x 10) = 252mw + 478.8mw + 10374mw = 11.10 watts note ? since the calculated power in example 2 is higher than the maximum power dissipation listed in section 3.1, a heat sink would be required.
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 57 6. component availability and ordering information the following table lists the msx package options and operating temperature ranges that are currently available. contact i-cube marketing for more up-to-date information. table 22 order information table 21 component availability device package code package pins temperature range availability msx532-tb792 tb 792 commercial now msx532-10tb792 tb 792 commercial contact i-cube marketing msx340-pb480 pb 480 commercial now MSX340-10PB480 pb 480 commercial contact i-cube marketing msxxxx-sspp###t package code package pin count speed grade tb - thin ball grid array (msx532) pb - ball grid array (msx340) blank - commercial (0 c to 70 c) t emperature range 792 (msx532) 480 (msx340) blank - 20ns 10 - 10ns number of i/o 532 (msx532) 340 (msx340)
msx family data sheet 58 [rev. 1.8] 2/28/01 i-cube, inc. 7. glossary array side: the signal and connections between the crosspoint array and the io buffer. bus repeater: a circuit operation of the io buffer that enables the msx device to pass data in both directions on an io device pin. the io buffer is placed in a disabled output state to the pin and to the crosspoint array. a forced low on either side of the io buffer will be transmitted to the other side of the io buffer and held until the forced low is changed to a force high. at the change of the forcing input, the io buffer will force the other side to a following high state and drive a high level out for a period of time. after the period of time, the io buffer will return to the disabled state. bypass: a jtag instruction that connects the previous chip to the next chip through a one bit data register to speed up programming of other chips in a jtag chain of devices. clock: four device corner inputs used to gate data into registers in the io buffer. the corner inputs serve two sides of the msx. this provides two choices for each io buffer register in and register out. the neighbor input can also be used as register clock and the clocks can be inverted. control register: a programmable register used to control various functions in programming and other circuit settings. all bits programmed in the jtag mode. rapid configure enable bit can be set with a high level on the rce pin during a reset of the circuits. crosspoint: a single cell containing two n channel transistors and two ram bits. the ram bits are connected in a master-slave configuration to provide an update for programming and changing program information all at once. each cell contains both an x and y reset to remove all ports connected to an addressed port in a single program cycle. crosspoint array: an array of crosspoint used to connect any port to any other port or any combination of other ports. the array has all redundant cell removed; there is a single crosspoint cell for each port to port connection. the reduced cell count is folded to provide a square array. the array has a diagonal line where the cells are rotated. data bit lines : a pair of signal lines used to write into and read out of crosspoint cells. the lines are pre- charged before a read and one is pulled low for a write. device id: a 32-bit register in the msx device with a wired identification. the id consists of a given number for the device and a revision history field. the identification is shifted out during jtag reset and the device id instruction in jtag mode. the id for the msx devices is 0x0000a89f. extest: a jtag instruction that samples i/o pin states and loads new i/o buffer states for testing device pin connections. the msx devices use a special test mode in extext to observe the buffer data on the pin side and the array side. a bit in the control register controls this mode. io buffer: the circuit that controls the driving of its associated pin and its port into and out of the crosspoint array. the buffer contains all the circuits to make it independent of the other io buffers. each buffer contains registers for input and output, driving circuits for input and output, sense for crosspoint array input, and ram bits to hold programmed data controlling the function of the buffer. input or output path: the signal flow from pin to array and array to pin. each path has a register with selectable clocks, drivers for the loaded outputs with selectable enables, and sense circuits to detect changes on either side of the io buffer. jtag: the joint test action group is a committee to standardize scan testing of devices. the jtag interface is referred to as ieee 1149.1. this is a five bit serial programming and testing method.
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 59 jtag sequence: the ordering of all the pins in a serial chain for driving and sensing signals on pins during extest and sample/preload. all pins except power and ground and the five jtag pins are in the serial string. next neighbor: input can be selected as the clock for the iob registers for data and clock pairing. the next higher port is the selected neighbor except for port 531, which uses port 0. pin side driver: the io buffer circuit that drives the device pin associated with that buffer. port: a name followed by a number to identify a pin on the device. ports are numbered from 531 to 0 on the msx device. in shifting sequence, port p000 is shifted in first and shifted out first. rapidconfigure: a parallel programming method for the msx devices. the rc mode uses 29 dedicated pins to program the crosspoint array and the io buffers. the 29 pins consist of an enable, a strobe, two instruction bits, four variable bits, and two ten-bit address fields. rce: a control pin of the msx device that is sampled during reset to determine if the device becomes active in the jtag or the rapid configure mode. this pin places the control register bit in the state to allow rc operations or not based on the voltage level of the rce pin. the jtag mode is always enabled and can set or clear the rc bit in the control register. trickle current: a very low current (~15 microamperes) used to pull unused or non-driven circuits to a stable high level. prevents signals from drifting between cmos thresholds and drawing currents from the power supply. in the case of bus repeater, the small trickle current provides a known high level on the pin and array side inputs.
msx family data sheet 60 [rev. 1.8] 2/28/01 i-cube, inc. revision history . table 23 revision history date/ version no. description 5/1/2000 revision 1.3 initial release of ? preliminary ? data sheet 6/30/2000 revision 1.4 converted data sheet from a word document to a framemaker document. corrected rcc[1] statement in 1.4.3 ? crosspoint programming ? . 10/16/00 revision 1.5 added msx340 pinout tables, package pinout drawing, package dimension drawings. changed verbiage throughout document to reflect msx family. added the -10 and the -15 device specifications to the ac electrical tables. updated ordering information. 12/1/00 revision 1.6 changed the -15 device to a -20 device in the ac electrical specifications table and modified the parameters for additional multicast mode, jtag clock frequency, and one way signal propagation delay. modified the rapidconfigure iob read and write cycles timing diagram. changed the update signal and relative descriptions from low (update#) to high (update) throughout entire document.corrected pinout drawings for the msx532 and msx340 to reflect the change to the update pin. modified component availability and ordering information tables. 2/20/2001 revision 1.7 changed ball name for aj26 from rst to trst# on msx340 pinout drawing and msx340 ? pinout by ball name ? table; added ? ...output data inversion mode... ? to op i/o port function in table 1. 2/26/01 revision 1.8 table 14 ? changed max parameters for nrz data rate from 200mb/s to 150mb/s, and registered input/output clock frequency from 100mhz to 75mhz; made specific references to product/package size on front page.
msx family data sheet i-cube, inc. [rev. 1.8] 2/28/01 61 8. product status definition i-cube ? is a registered trademark and rapidconnect, rapidconfigure, activearray, implieddisconnect, iq, iqx, msx, msxpro, ocx, ocxpro and psx are trademarks of i-cube, inc. all other trademarks or registered trademarks are the property of their respective holders. i-cube, inc., does not assume any liability arising out of the applications or use of the product described herein; nor does it convey any license under its patents, copyright rights or any rights of others. the information contained in this document is believed to be current and accurate as of the publication date. i-cube reserves the right to make changes, at any time, in order to improve reliability, function, performance or design in order to supply the best product possible. i-cube assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. this product is protected under the u.s. patents: 5202593, 5282271, 5426738, 5428750, 5428800, 5465056, 5530814, 5559971, 5625780, 5710550, 5717871, 5734334, 5781717, 5790048. additional patents pending. msx family data sheet ? rev 1.8, february 2001 copyright ? 1992-2001 i-cube, inc. all rights reserved. unpublished ? rights reserved under the copyright laws of the united states. use of copyright notices is precautionary and does not imply publication or disclosure. i-cube ? , inc. 2605 s. winchester blvd. campbell, ca 95008 usa phone: +(408) 341-1888 msx family data sheet fax: +(408) 341-1899 revision 1.8, february 2001 email: marketing@icube.com document#: mkt-msxfamily-ds_rev+1+dot+8 internet: http://www.icube.com data sheet identification product status definition advanced formative or in design this data sheet contains the design specifications for product development. specification may change in any manner without notice. preliminary preproduction product this data sheet contains the preliminary data, and supplementary data will be published at a later date. i-cube reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. no identification full production this data sheet contains final specifications. i-cube reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. obsolete no longer in production this data sheet contains specifications for a product that has been discontinued by i-cube. the data sheet is provided for reference information only.

▲Up To Search▲

Price & Availability of MSX340-10PB480

	To Download MSX340-10PB480 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .